| /kernel/linux/linux-5.10/arch/nios2/mm/ |
| D | tlb.c | 22 ((((1UL << (cpuinfo.tlb_ptr_sz - cpuinfo.tlb_num_ways_log2))) - 1) \
38 return ((addr | 0xC0000000UL) >> PAGE_SHIFT) << 2; in pteaddr_invalid()
47 unsigned int way; in replace_tlb_one_pid() local
50 /* remember pid/way until we return. */ in replace_tlb_one_pid()
53 WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2); in replace_tlb_one_pid()
55 for (way = 0; way < cpuinfo.tlb_num_ways; way++) { in replace_tlb_one_pid()
60 tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT); in replace_tlb_one_pid()
64 if (((pteaddr >> 2) & 0xfffff) != (addr >> PAGE_SHIFT)) in replace_tlb_one_pid()
73 (way << TLBMISC_WAY_SHIFT); in replace_tlb_one_pid()
90 pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr); in flush_tlb_one_pid()
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| /kernel/linux/linux-5.10/arch/x86/kernel/cpu/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0
27 #define LVL_1_DATA 2
45 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
46 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
48 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
49 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
50 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
51 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
52 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
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| D | intel.c | 1 // SPDX-License-Identifier: GPL-2.0
18 #include <asm/intel-family.h>
61 * Processors which have self-snooping capability can handle conflicting
69 switch (c->x86_model) { in check_memory_type_self_snoop_errata()
101 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
103 switch (c->x86_model) { in probe_xeon_phi_r3mwait()
125 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
126 * - https://kb.vmware.com/s/article/52345
127 * - Microcode revisions observed in the wild
128 * - Release note from 20180108 microcode release
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | bcm2837.dtsi | 2 #include "bcm2835-common.dtsi"
3 #include "bcm2835-rpi-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a53-pmu";
24 interrupt-parent = <&local_intc>;
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| /kernel/linux/linux-5.10/arch/openrisc/include/asm/ |
| D | spr_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
29 #define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS)
43 #define SPR_CPUCFGR (SPRGROUP_SYS + 2)
71 #define SPR_DTLBEIR (SPRGROUP_DMMU + 2)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
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| /kernel/linux/linux-5.10/arch/x86/crypto/ |
| D | twofish_glue_3way.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Glue Code for 3-way parallel assembler optimized version of Twofish
25 return twofish_setkey(&tfm->base, key, keylen); in twofish_setkey_skcipher()
41 u128 ivs[2]; in twofish_dec_blk_cbc_3way()
51 u128_xor(&dst[2], &dst[2], &ivs[1]); in twofish_dec_blk_cbc_3way()
81 dst[2] = src[2]; in twofish_enc_blk_ctr_3way()
88 le128_to_be128(&ctrblks[2], iv); in twofish_enc_blk_ctr_3way()
96 .num_funcs = 2,
97 .fpu_blocks_limit = -1,
109 .num_funcs = 2,
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| D | blowfish-x86_64-asm_64.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 .file "blowfish-x86_64-asm.S"
15 #define s0 ((16 + 2) * 4)
16 #define s1 ((16 + 2 + (1 * 256)) * 4)
17 #define s2 ((16 + 2 + (2 * 256)) * 4)
18 #define s3 ((16 + 2 + (3 * 256)) * 4)
57 * 1-way blowfish
83 movq p+4*(n-1)(CTX), RT0; \
122 round_enc(2);
177 4-way blowfish, four blocks parallel
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| /kernel/linux/linux-5.10/arch/mips/kernel/ |
| D | bmips_5xxx_init.S | 7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
64 #define CP0_DCACHE_TAG_LO $28, 2
68 #define CP0_DCACHE_TAG_HI $29, 2
84 #define BRCM_ZSC_REQ_BUFFER_REG 2 << 3
107 .align 2
112 * Description: compute the I-cache size and I-cache line size
126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
131 * vi) 0x5 - 0x7: Reserved.
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| /kernel/linux/linux-5.10/arch/arc/mm/ |
| D | tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
11 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
13 * = page-fault thrice as fast (75 usec to 28 usec)
18 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * -MMU v2/v3 BCRs decoded differently
23 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
24 * -tlb_entry_erase( ) can be void
25 * -local_flush_tlb_range( ):
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| /kernel/linux/linux-5.10/arch/powerpc/mm/nohash/ |
| D | tlb_low.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level functions for performing various
7 * This file implements the following functions for all no-hash
11 * - tlbil_va
12 * - tlbil_pid
13 * - tlbil_all
14 * - tlbivax_bcast
18 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
29 #include <asm/asm-offsets.h>
32 #include <asm/asm-compat.h>
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| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | cache-xsc3l2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
44 int set, way; in xsc3_l2_inv_all() local
49 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_inv_all()
50 set_way = (way << 29) | (set << 5); in xsc3_l2_inv_all()
51 __asm__("mcr p15, 1, %0, c7, c11, 2" : : "r"(set_way)); in xsc3_l2_inv_all()
61 if (va != -1) in l2_unmap_va()
70 unsigned long pa_offset = pa << (32 - PAGE_SHIFT); in l2_map_va()
71 if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) { in l2_map_va()
80 return va + (pa_offset >> (32 - PAGE_SHIFT)); in l2_map_va()
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| D | cache-v7m.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v7m.S
5 * Based on linux/arch/arm/mm/cache-v7.S
19 #include "proc-macros.S"
48 * dcisw: Invalidate data cache by set/way
55 * dccisw: Clean and invalidate data cache by set/way
129 and r3, r1, r0, lsr #3 @ NumWays - 1
137 1: sub r2, r2, #1 @ NumSets--
139 2: subs r3, r3, #1 @ Temp--
144 bgt 2b
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| /kernel/linux/linux-5.10/arch/mips/include/asm/octeon/ |
| D | cvmx-l2c.h | 7 * Copyright (c) 2003-2017 Cavium, Inc.
10 * it under the terms of the GNU General Public License, Version 2, as
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
44 #define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
52 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
72 CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
131 CVMX_L2C_TAD_EVENT_TAG_MISS = 2,
183 * Return the L2 Cache way partitioning for a given core.
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| /kernel/linux/linux-5.10/arch/mips/mm/ |
| D | cerr-sb1.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
73 printk(" multiple-buserr"); in breakout_errctl()
80 printk(" tag-parity"); in breakout_cerri()
82 printk(" data-parity"); in breakout_cerri()
114 printk(" multi-err"); in breakout_cerrd()
116 printk(" tag-state"); in breakout_cerrd()
118 printk(" tag-address"); in breakout_cerrd()
120 printk(" data-SBE"); in breakout_cerrd()
122 printk(" data-DBE"); in breakout_cerrd()
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| /kernel/linux/linux-5.10/Documentation/admin-guide/ |
| D | devices.txt | 1 0 Unnamed devices (e.g. non-device mounts)
7 2 = /dev/kmem Kernel virtual memory access
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
49 2 block Floppy disks
52 2 = /dev/fd2 Controller 0, drive 2, autodetect
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| /kernel/linux/linux-5.10/arch/arm/include/asm/ |
| D | v7m.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
21 #define V7M_SCB_AIRCR_SYSRESETREQ (1 << 2)
24 #define V7M_SCB_SCR_SLEEPDEEP (1 << 2)
48 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
49 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
52 #define EXC_RET_THREADMODE_PROCESSSTACK (3 << 2)
61 /* Memory-mapped MPU registers for M-class */
65 #define MPU_CTRL_PRIVDEFENA (1 << 2)
80 #define V7M_SCB_ICIALLU 0x250 /* I-cache invalidate all to PoU */
81 #define V7M_SCB_ICIMVAU 0x258 /* I-cache invalidate by MVA to PoU */
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/powernv/ |
| D | subcore.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
30 * A core can be in one of three states, unsplit, 2-way split, and 4-way split.
35 * ------------|------------------
37 * 2-way split | 2
38 * 4-way split | 4
44 * ----------------------------
46 * ----------------------------
47 * Thread | 0 1 2 3 4 5 6 7 |
48 * ----------------------------
50 * 2-way split:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mux/ |
| D | mux-controller.txt | 11 space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
12 0-7 for an 8-way multiplexer, etc.
16 ---------
19 want to use with a property containing a 'mux-ctrl-list':
21 mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
22 single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
23 mux-ctrl-phandle : phandle to mux controller node
24 mux-ctrl-specifier : array of #mux-control-cells specifying the
27 Mux controller properties should be named "mux-controls". The exact meaning of
29 each consumer. An optional property "mux-control-names" may contain a list of
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| /kernel/linux/linux-5.10/arch/arc/include/asm/ |
| D | tlb-mmu1.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
20 ; Calculate set index for 2-way MMU
21 ; -avoiding use of GetIndex from MMU
22 ; and its unpleasant LFSR pseudo-random sequence
26 ; -- jh_ex_way_set not cleared on startup
30 ; -- should be in cache since in same line
38 or.nz r0,r0,1 ; set way bit
44 ; JH hack #2
45 ; Faster than hack #1 in non-thrash case, but hard-coded for 2-way MMU
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| /kernel/linux/linux-5.10/arch/sh/mm/ |
| D | cache-sh2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/sh/mm/cache-sh2.c
23 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
24 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2__flush_wback_region()
25 & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
28 int way; in sh2__flush_wback_region() local
29 for (way = 0; way < 4; way++) { in sh2__flush_wback_region()
30 unsigned long data = __raw_readl(addr | (way << 12)); in sh2__flush_wback_region()
33 __raw_writel(data, addr | (way << 12)); in sh2__flush_wback_region()
44 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_purge_region()
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| D | cache-debugfs.c | 27 unsigned int cache_type = (unsigned int)file->private; in cache_seq_show()
29 unsigned int waysize, way; in cache_seq_show() local
55 waysize = cache->sets; in cache_seq_show()
64 waysize <<= cache->entry_shift; in cache_seq_show()
66 for (way = 0; way < cache->ways; way++) { in cache_seq_show()
70 seq_printf(file, "-----------------------------------------\n"); in cache_seq_show()
71 seq_printf(file, "Way %d\n", way); in cache_seq_show()
72 seq_printf(file, "-----------------------------------------\n"); in cache_seq_show()
76 addr += cache->linesz, line++) { in cache_seq_show()
85 line, data & 2 ? 'U' : ' ', in cache_seq_show()
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| /kernel/linux/linux-5.10/arch/xtensa/include/asm/ |
| D | tlbflush.h | 6 * Copyright (C) 2001 - 2013 Tensilica Inc.
27 * - flush_tlb_all() flushes all processes TLB entries
28 * - flush_tlb_mm(mm) flushes the specified mm context TLB entries
29 * - flush_tlb_page(mm, vmaddr) flushes a single page
30 * - flush_tlb_range(mm, start, end) flushes a range of pages
130 static inline void write_dtlb_entry (pte_t entry, int way) in write_dtlb_entry() argument
133 : : "r" (way), "r" (entry) ); in write_dtlb_entry()
136 static inline void write_itlb_entry (pte_t entry, int way) in write_itlb_entry() argument
139 : : "r" (way), "r" (entry) ); in write_itlb_entry()
146 invalidate_dtlb_entry (DTLB_WAY_PGD+2); in invalidate_page_directory()
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| /kernel/linux/linux-5.10/drivers/staging/gs_fpgaboot/ |
| D | README | 9 2. BACKGROUND
16 - Download Xilinx FPGA firmware
17 - This module downloads Xilinx FPGA firmware using gpio pins.
19 2. BACKGROUND
23 a dedicated device or CPU assisted way (serial or parallel).
24 This driver provides a way to download FPGA firmware.
28 - load Xilinx FPGA bitstream format[1] firmware image file using
30 - program the Xilinx FPGA using SelectMAP (parallel) mode [2]
31 - FPGA prgram is done by gpio based bit-banging, as an example
32 - platform independent file: gs_fpgaboot.c
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| /kernel/linux/linux-5.10/Documentation/ia64/ |
| D | efirtc.rst | 13 the IA-64 platform.
23 2. Design Decisions
28 portable way, the CMOS clock. A program like /sbin/hwclock uses such a clock
31 Because we wanted to minimize the impact on existing user-level apps using
38 EFI uses a slightly different way of representing the time, noticeably
39 the reference date is different. Year is the using the full 4-digit format.
41 expose this new way of representing time. Instead we use something very
43 One of the reasons for doing it this way is to allow for EFI to still evolve
48 ioctl()s. The other is read-only via the /proc filesystem.
94 # /sbin/hwclock --show
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| /kernel/linux/linux-5.10/arch/mips/cavium-octeon/executive/ |
| D | cvmx-l2c.c | 7 * Copyright (c) 2003-2017 Cavium, Inc.
10 * it under the terms of the GNU General Public License, Version 2, as
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Implementation of the Level 2 Cache (L2C) control,
36 #include <asm/octeon/cvmx-l2c.h>
37 #include <asm/octeon/cvmx-spinlock.h>
43 * NOTE: This only protects calls from within a single application -
55 return -1; in cvmx_l2c_get_core_way_partition()
89 valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1; in cvmx_l2c_set_core_way_partition()
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