| /kernel/linux/linux-5.10/arch/mips/boot/dts/loongson/ |
| D | ls7a-pch.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "simple-bus";
6 #address-cells = <2>;
7 #size-cells = <2>;
13 pic: interrupt-controller@10000000 {
14 compatible = "loongson,pch-pic-1.0";
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
18 loongson,pic-base-vec = <0>;
19 #interrupt-cells = <2>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | mediatek-pcie.txt | 4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 - device_type: Must be "pci"
11 - reg: Base addresses and lengths of the PCIe subsys and root ports.
12 - reg-names: Names of the above areas to use during resource lookup.
13 - #address-cells: Address representation for root ports (must be 3)
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| D | xilinx-pcie.txt | 4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
8 - compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
9 - reg: Should contain AXI PCIe registers location and length
10 - device_type: must be "pci"
11 - interrupts: Should contain AXI PCIe interrupt
12 - interrupt-map-mask,
13 interrupt-map: standard PCI properties to define the mapping of the
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| D | mvebu-pci.txt | 5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
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| D | ralink,rt3883-pci.txt | 7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
35 - interrupt-controller: identifies the node as an interrupt controller
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| D | xilinx-versal-cpm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
17 const: xlnx,versal-cpm-host-1.00
21 - description: Configuration space region and bridge registers.
22 - description: CPM system level control and status registers.
24 reg-names:
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| D | faraday,ftpci100.txt | 5 plain and dual PCI. The plain version embeds a cascading interrupt controller
7 chips interrupt controller.
14 - compatible: ranging from specific to generic, should be one of
15 "cortina,gemini-pci", "faraday,ftpci100"
16 "cortina,gemini-pci-dual", "faraday,ftpci100-dual"
18 "faraday,ftpci100-dual"
19 - reg: memory base and size for the host bridge
20 - #address-cells: set to <3>
21 - #size-cells: set to <2>
22 - #interrupt-cells: set to <1>
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| D | brcm,iproc-pcie.txt | 4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
18 mapping of the PCIe interface to interrupt numbers
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| D | rockchip-pcie-host.txt | 4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
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| D | versatile.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 - $ref: /schemas/pci/pci-bus.yaml#
20 const: arm,versatile-pci
24 - description: Versatile-specific registers
25 - description: Self Config space
26 - description: Config space
31 "#interrupt-cells": true
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| D | intel-gw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
16 const: intel,lgm-pcie
18 - compatible
23 - const: intel,lgm-pcie
24 - const: snps,dw-pcie
29 "#address-cells":
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| D | altera-pcie.txt | 4 - compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
5 - reg: a list of physical base address and length for TXS and CRA.
6 For "altr,pcie-root-port-2.0", additional HIP base address and length.
7 - reg-names: must include the following entries:
10 "Hip": Hard IP region (if "altr,pcie-root-port-2.0")
11 - interrupts: specifies the interrupt source of the parent interrupt
12 controller. The format of the interrupt specifier depends
13 on the parent interrupt controller.
14 - device_type: must be "pci"
15 - #address-cells: set to <3>
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| D | xilinx-nwl-pcie.txt | 4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
5 - #address-cells: Address representation for root ports, set to <3>
6 - #size-cells: Size representation for root ports, set to <2>
7 - #interrupt-cells: specifies the number of cells needed to encode an
8 interrupt source. The value must be 1.
9 - reg: Should contain Bridge, PCIe Controller registers location,
11 - reg-names: Must include the following entries:
15 - device_type: must be "pci"
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
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| D | aardvark-pci.txt | 8 - compatible: Should be "marvell,armada-3700-pcie"
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
11 - #address-cells: set to <3>
12 - #size-cells: set to <2>
13 - device_type: set to "pci"
14 - ranges: ranges for the PCI memory and I/O regions
15 - #interrupt-cells: set to <1>
16 - msi-controller: indicates that the PCIe controller can itself
18 - msi-parent: pointer to the MSI controller to be used
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| /kernel/linux/linux-5.10/Documentation/core-api/irq/ |
| D | irq-domain.rst | 2 The irq_domain interrupt number mapping library
7 This is simple when there is only one interrupt controller, but in
8 systems with multiple interrupt controllers the kernel must ensure
9 that each one gets assigned non-overlapping allocations of Linux
12 The number of interrupt controllers registered as unique irqchips
15 mechanisms as the IRQ core system by modelling their interrupt
16 handlers as irqchips, i.e. in effect cascading interrupt controllers.
18 Here the interrupt number loose all kind of correspondence to
19 hardware interrupt numbers: whereas in the past, IRQ numbers could
21 interrupt controller (i.e. the component actually fireing the
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | armada-xp-mv78260.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
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| D | armada-xp-mv78460.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
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| D | armada-xp-mv78230.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
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| D | armada-385.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
30 compatible = "arm,cortex-a9";
37 compatible = "marvell,armada-370-pcie";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | renesas,rza1-irqc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A1 Interrupt Controller
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
17 - NMI edge select.
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| D | fsl,ls-extirq.txt | 4 the polarity of certain external interrupt lines.
10 - compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
11 - #interrupt-cells: Must be 2. The first element is the index of the
12 external interrupt line. The second element is the trigger type.
13 - #address-cells: Must be 0.
14 - interrupt-controller: Identifies the node as an interrupt controller
15 - reg: Specifies the Interrupt Polarity Control Register (INTPCR) in
17 - interrupt-map: Specifies the mapping from external interrupts to GIC
19 - interrupt-map-mask: Must be <0xffffffff 0>.
23 compatible = "fsl,ls1021a-scfg", "syscon";
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| /kernel/linux/linux-5.10/drivers/of/ |
| D | irq.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Copyright (C) 1996-2001 Cort Dougan
13 * device tree to actual irq numbers on an interrupt controller
29 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
30 * @dev: Device node of the device whose interrupt is to be mapped
31 * @index: Index of the interrupt to map
48 * of_irq_find_parent - Given a device node, find its interrupt parent node
51 * Returns a pointer to the interrupt parent node, or NULL if the interrupt
63 if (of_property_read_u32(child, "interrupt-parent", &parent)) { in of_irq_find_parent()
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| /kernel/linux/linux-5.10/drivers/dma/ipu/ |
| D | ipu_irq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/dma/ipu-dma.h>
20 * Register read / write - shall be inlined by the compiler
24 return __raw_readl(ipu->reg_ipu + reg); in ipu_read_reg()
29 __raw_writel(value, ipu->reg_ipu + reg); in ipu_write_reg()
95 struct ipu_irq_map *map = irq_data_get_irq_chip_data(d); in ipu_irq_unmask() local
102 bank = map->bank; in ipu_irq_unmask()
105 pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq); in ipu_irq_unmask()
109 reg = ipu_read_reg(bank->ipu, bank->control); in ipu_irq_unmask()
110 reg |= (1UL << (map->source & 31)); in ipu_irq_unmask()
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-ingenic-tcu.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/interrupt.h>
11 #include <linux/mfd/ingenic-tcu.h>
17 struct regmap *map; member
26 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); in ingenic_tcu_intc_cascade()
29 struct regmap *map = gc->private; in ingenic_tcu_intc_cascade() local
33 regmap_read(map, TCU_REG_TFR, &irq_reg); in ingenic_tcu_intc_cascade()
34 regmap_read(map, TCU_REG_TMR, &irq_mask); in ingenic_tcu_intc_cascade()
50 struct regmap *map = gc->private; in ingenic_tcu_gc_unmask_enable_reg() local
51 u32 mask = d->mask; in ingenic_tcu_gc_unmask_enable_reg()
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| /kernel/linux/linux-5.10/drivers/base/regmap/ |
| D | regmap-irq.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/interrupt.h>
24 struct regmap *map; member
52 return &data->chip->irqs[irq]; in irq_to_regmap_irq()
59 mutex_lock(&d->lock); in regmap_irq_lock()
66 if (d->chip->mask_writeonly) in regmap_irq_update_bits()
67 return regmap_write_bits(d->map, reg, mask, val); in regmap_irq_update_bits()
69 return regmap_update_bits(d->map, reg, mask, val); in regmap_irq_update_bits()
75 struct regmap *map = d->map; in regmap_irq_sync_unlock() local
81 if (d->chip->runtime_pm) { in regmap_irq_sync_unlock()
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