Home
last modified time | relevance | path

Searched refs:rad_info (Results 1 – 25 of 36) sorted by relevance

12

/third_party/mesa3d/src/amd/vulkan/
Dsi_cmd_buffer.c40 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1); in si_write_harvested_raster_configs()
44 ac_get_harvested_configs(&physical_device->rad_info, raster_config, &raster_config_1, in si_write_harvested_raster_configs()
49 if (physical_device->rad_info.gfx_level < GFX7) in si_write_harvested_raster_configs()
61 if (physical_device->rad_info.gfx_level < GFX7) in si_write_harvested_raster_configs()
70 if (physical_device->rad_info.gfx_level >= GFX7) in si_write_harvested_raster_configs()
77 const struct radeon_info *info = &device->physical_device->rad_info; in si_emit_compute()
85 S_00B834_DATA(device->physical_device->rad_info.address32_hi >> 8)); in si_emit_compute()
93 if (device->physical_device->rad_info.gfx_level >= GFX7) { in si_emit_compute()
108 if (device->physical_device->rad_info.gfx_level >= GFX9 && in si_emit_compute()
109 device->physical_device->rad_info.gfx_level < GFX11) { in si_emit_compute()
[all …]
Dradv_sqtt.c42 return device->physical_device->rad_info.cu_mask[se][0] == 0; in radv_se_is_disabled()
54 if (device->physical_device->rad_info.gfx_level == GFX10_3) in gfx10_get_thread_trace_ctrl()
57 if (device->physical_device->rad_info.has_sqtt_auto_flush_mode_bug) in gfx10_get_thread_trace_ctrl()
68 cs, device->physical_device->rad_info.gfx_level, NULL, 0, in radv_emit_wait_for_idle()
69 family == AMD_IP_COMPUTE && device->physical_device->rad_info.gfx_level >= GFX7, in radv_emit_wait_for_idle()
83 struct radeon_info *rad_info = &device->physical_device->rad_info; in radv_emit_thread_trace_start() local
84 unsigned max_se = rad_info->max_se; in radv_emit_thread_trace_start()
88 uint64_t data_va = ac_thread_trace_get_data_va(rad_info, &device->thread_trace, va, se); in radv_emit_thread_trace_start()
90 int first_active_cu = ffs(device->physical_device->rad_info.cu_mask[se][0]); in radv_emit_thread_trace_start()
100 if (device->physical_device->rad_info.gfx_level >= GFX10) { in radv_emit_thread_trace_start()
[all …]
Dradv_device.c117 enum radeon_family family = pdevice->rad_info.family; in radv_device_get_cache_uuid()
167 return MIN2((uint64_t)device->rad_info.vram_size_kb * 1024, (uint64_t)ov << 20); in radv_get_adjusted_vram_size()
168 return (uint64_t)device->rad_info.vram_size_kb * 1024; in radv_get_adjusted_vram_size()
174 …return MIN2(radv_get_adjusted_vram_size(device), (uint64_t)device->rad_info.vram_vis_size_kb * 102… in radv_get_visible_vram_size()
181 return total_size - MIN2(total_size, (uint64_t)device->rad_info.vram_vis_size_kb * 1024); in radv_get_vram_size()
196 uint64_t gtt_size = (uint64_t)device->rad_info.gart_size_kb * 1024; in radv_physical_device_init_mem_types()
202 if (!device->rad_info.has_dedicated_vram) { in radv_physical_device_init_mem_types()
208 visible_vram_size = align64((total_size * 2) / 3, device->rad_info.gart_page_size); in radv_physical_device_init_mem_types()
291 if (device->rad_info.has_l2_uncached) { in radv_physical_device_init_mem_types()
384 return pdev->rad_info.gfx_level == GFX10_3 && !radv_thread_trace_enabled(); in radv_perf_query_supported()
[all …]
Dradv_image.c55 device->physical_device->rad_info.gfx_level <= GFX8) { in radv_choose_tiling()
73 if (device->physical_device->rad_info.gfx_level < GFX8) in radv_use_tc_compat_htile_for_image()
89 if (device->physical_device->rad_info.gfx_level < GFX9) { in radv_use_tc_compat_htile_for_image()
113 if (device->physical_device->rad_info.gfx_level >= GFX9) in radv_surface_has_scanout()
182 if (!radv_dcc_formats_compatible(pdev->rad_info.gfx_level, format, in radv_are_formats_dcc_compatible()
233 if (device->physical_device->rad_info.gfx_level < GFX8) in radv_use_dcc_for_image_early()
250 (device->physical_device->rad_info.gfx_level < GFX10 || in radv_use_dcc_for_image_early()
272 if (device->physical_device->rad_info.gfx_level < GFX10) { in radv_use_dcc_for_image_early()
279 device->physical_device->rad_info.gfx_level == GFX9) in radv_use_dcc_for_image_early()
321 return ac_surface_supports_dcc_image_stores(device->physical_device->rad_info.gfx_level, in radv_image_use_dcc_image_stores()
[all …]
Dradv_shader.c85 .lower_ffma16 = split_fma || device->rad_info.gfx_level < GFX9, in get_nir_options_for_stage()
86 .lower_ffma32 = split_fma || device->rad_info.gfx_level < GFX10_3, in get_nir_options_for_stage()
91 .lower_iadd_sat = device->rad_info.gfx_level <= GFX8, in get_nir_options_for_stage()
96 .has_sdot_4x8 = device->rad_info.has_accelerated_dot_product, in get_nir_options_for_stage()
97 .has_udot_4x8 = device->rad_info.has_accelerated_dot_product, in get_nir_options_for_stage()
98 .has_dot_2x16 = device->rad_info.has_accelerated_dot_product, in get_nir_options_for_stage()
729 .float16 = device->physical_device->rad_info.has_packed_math_16bit, in radv_shader_spirv_to_nir()
774 .fragment_shading_rate = device->physical_device->rad_info.gfx_level >= GFX10_3, in radv_shader_spirv_to_nir()
879 if (device->physical_device->rad_info.gfx_level == GFX6) { in radv_shader_spirv_to_nir()
960 bool gfx7minus = device->physical_device->rad_info.gfx_level <= GFX7; in radv_shader_spirv_to_nir()
[all …]
Dradv_pipeline.c289 MIN2(max_stage_waves, 4 * device->physical_device->rad_info.num_cu * in radv_pipeline_init_scratch()
477 bool use_rbplus = device->physical_device->rad_info.rbplus_allowed; in radv_choose_spi_color_format()
700 const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; in radv_pipeline_init_blend_state()
840 if (device->physical_device->rad_info.has_rbplus) { in radv_pipeline_init_blend_state()
853 (device->physical_device->rad_info.gfx_level >= GFX11 && blend.blend_enable_4bit)) in radv_pipeline_init_blend_state()
1081 unsigned num_tile_pipes = pdevice->rad_info.num_tile_pipes; in radv_pipeline_init_multisample_state()
1143 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pdevice->rad_info.gfx_level >= GFX9) | in radv_pipeline_init_multisample_state()
1175 S_028BE0_COVERED_CENTROID_IS_CENTER(pdevice->rad_info.gfx_level >= GFX10_3); in radv_pipeline_init_multisample_state()
1416 …if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && pdevice->rad_info.gfx_level <= GFX8) in radv_compute_ia_multi_vgt_param_helpers()
1435 if ((pdevice->rad_info.family == CHIP_TAHITI || in radv_compute_ia_multi_vgt_param_helpers()
[all …]
Dradv_debug.c87 ac_vm_fault_occured(device->physical_device->rad_info.gfx_level, &device->dmesg_timestamp, NULL); in radv_init_trace()
117 ac_dump_reg(f, device->physical_device->rad_info.gfx_level, offset, value, ~0); in radv_dump_mmapped_reg()
123 struct radeon_info *info = &device->physical_device->rad_info; in radv_dump_debug_registers()
197 enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; in radv_dump_descriptor_set()
372 enum amd_gfx_level gfx_level = pipeline->device->physical_device->rad_info.gfx_level; in radv_dump_annotated_shaders()
619 struct radeon_info *info = &device->physical_device->rad_info; in radv_dump_device_name()
649 device->physical_device->rad_info.gfx_level >= GFX10 ? "gfx_0.0.0" : "gfx"); in radv_dump_umr_ring()
667 device->physical_device->rad_info.gfx_level >= GFX10 ? "gfx_0.0.0" : "gfx"); in radv_dump_umr_waves()
696 vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.gfx_level, in radv_check_gpu_hangs()
807 ac_print_gpu_info(&device->physical_device->rad_info, f); in radv_check_gpu_hangs()
[all …]
Dradv_cs.h123 if (pdevice->rad_info.gfx_level < GFX10) in radeon_set_sh_reg_idx()
178 if (pdevice->rad_info.gfx_level < GFX9 || in radeon_set_uconfig_reg_idx()
179 (pdevice->rad_info.gfx_level == GFX9 && pdevice->rad_info.me_fw_version < 26)) in radeon_set_uconfig_reg_idx()
199 bool filter_cam_workaround = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10 && in radeon_set_perfctr_reg()
Dradv_formats.c161 if (pdevice->rad_info.gfx_level <= GFX8 && pdevice->rad_info.family != CHIP_STONEY) { in radv_translate_vertex_format()
600 return physical_device->rad_info.gfx_level >= GFX10_3; in radv_is_storage_image_format_supported()
641 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32 && pdevice->rad_info.gfx_level < GFX10_3) in radv_is_colorbuffer_format_supported()
686 return physical_device->rad_info.family == CHIP_VEGA10 || in radv_device_supports_etc()
687 physical_device->rad_info.family == CHIP_RAVEN || in radv_device_supports_etc()
688 physical_device->rad_info.family == CHIP_RAVEN2 || in radv_device_supports_etc()
689 physical_device->rad_info.family == CHIP_STONEY; in radv_device_supports_etc()
1258 ac_get_supported_modifiers(&dev->rad_info, &radv_modifier_options, in radv_list_drm_format_modifiers()
1267 ac_get_supported_modifiers(&dev->rad_info, &radv_modifier_options, in radv_list_drm_format_modifiers()
1315 ac_get_supported_modifiers(&dev->rad_info, &radv_modifier_options, in radv_list_drm_format_modifiers_2()
[all …]
Dradv_sdma_copy_image.c85 …uint32_t ib_pad_dw_mask = cmd_buffer->device->physical_device->rad_info.ib_pad_dw_mask[AMD_IP_SDMA… in radv_sdma_v4_v5_copy_image_to_buffer()
124 bool is_v5 = device->physical_device->rad_info.gfx_level >= GFX10; in radv_sdma_v4_v5_copy_image_to_buffer()
166 radv_translate_format_to_hw(&device->physical_device->rad_info, image->vk.format, &hw_fmt, in radv_sdma_v4_v5_copy_image_to_buffer()
194 assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9); in radv_sdma_copy_image()
Dradv_cmd_buffer.c356 cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7; in radv_cmd_buffer_uses_mec()
543 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX7) { in radv_reset_cmd_buffer()
553 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9 && in radv_reset_cmd_buffer()
555 unsigned num_db = cmd_buffer->device->physical_device->rad_info.max_render_backends; in radv_reset_cmd_buffer()
567 if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) { in radv_reset_cmd_buffer()
638 struct radeon_info *rad_info = &cmd_buffer->device->physical_device->rad_info; in radv_cmd_buffer_upload_alloc() local
644 unsigned line_size = rad_info->gfx_level >= GFX10 ? 64 : 32; in radv_cmd_buffer_upload_alloc()
731 si_cs_emit_cache_flush(ace_cs, cmd_buffer->device->physical_device->rad_info.gfx_level, NULL, 0, in radv_ace_internal_cache_flush()
774 cmd_buffer->cs, cmd_buffer->device->physical_device->rad_info.gfx_level, in radv_flush_gfx2ace_semaphore()
828 si_cs_emit_write_event_eop(ace_cs, cmd_buffer->device->physical_device->rad_info.gfx_level, in radv_ace_internal_finalize()
[all …]
Dradv_perfcounter.c80 … S_036020_SPM_PERFMON_STATE(device->physical_device->rad_info.never_stop_sq_perf_counters ? in radv_perfcounter_emit_spm_stop()
213 CONSTANT(pdev->rad_info.num_simd_per_compute_unit * pdev->rad_info.num_cu)
214 #define CTR_NUM_CUS CONSTANT(pdev->rad_info.num_cu)
259 if (pdev->rad_info.gfx_level >= GFX10_3) { in radv_query_perfcounter_descs()
285 if (pdev->rad_info.gfx_level >= GFX10_3) { in radv_query_perfcounter_descs()
366 ((ac_block->b->b->flags & AC_PC_BLOCK_SE) ? pdevice->rad_info.max_se : 1); in radv_pc_get_num_instances()
546 se_end = cmd_buffer->device->physical_device->rad_info.max_se; in radv_pc_sample_block()
744 si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.gfx_level, in radv_pc_end_query()
Dradv_wsi.c61 if (device->physical_device->rad_info.gfx_level >= GFX9 && in radv_wsi_get_prime_blit_queue()
99 physical_device->wsi_device.supports_modifiers = physical_device->rad_info.gfx_level >= GFX9; in radv_init_wsi()
Dradv_query.c115 unsigned enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask; in build_occlusion_query_shader()
116 unsigned db_count = device->physical_device->rad_info.max_render_backends; in build_occlusion_query_shader()
1101 pool->stride = 16 * device->physical_device->rad_info.max_render_backends; in radv_CreateQueryPool()
1228 uint32_t db_count = device->physical_device->rad_info.max_render_backends; in radv_GetQueryPoolResults()
1229 uint32_t enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask; in radv_GetQueryPoolResults()
1521 unsigned enabled_rb_mask = cmd_buffer->device->physical_device->rad_info.enabled_rb_mask; in radv_CmdCopyQueryPoolResults()
1774 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) { in emit_begin_query()
1776 BITFIELD64_MASK(cmd_buffer->device->physical_device->rad_info.max_render_backends); in emit_begin_query()
1788 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) { in emit_begin_query()
1878 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) { in emit_end_query()
[all …]
Dradv_device_generated_commands.c86 if (pipeline->base.device->physical_device->rad_info.has_gfx9_scissor_bug) { in radv_get_sequence_size()
477 if (dev->physical_device->rad_info.gfx_level == GFX9) in build_dgc_prepare_shader()
479 else if (dev->physical_device->rad_info.gfx_level != GFX8) in build_dgc_prepare_shader()
492 if (dev->physical_device->rad_info.gfx_level != GFX8) { in build_dgc_prepare_shader()
505 if (dev->physical_device->rad_info.gfx_level >= GFX10) { in build_dgc_prepare_shader()
832 if (dev->physical_device->rad_info.gfx_level >= GFX9) { in build_dgc_prepare_shader()
834 if (dev->physical_device->rad_info.gfx_level < GFX9 || in build_dgc_prepare_shader()
835 (dev->physical_device->rad_info.gfx_level == GFX9 && in build_dgc_prepare_shader()
836 dev->physical_device->rad_info.me_fw_version < 26)) in build_dgc_prepare_shader()
1152 !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug) in radv_prepare_dgc()
Dradv_meta_dcc_retile.c63 nir_ssa_def *src = ac_nir_dcc_addr_from_coord(&b, &dev->physical_device->rad_info, surf->bpe, in build_dcc_retile_compute_shader()
68 &b, &dev->physical_device->rad_info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation, in build_dcc_retile_compute_shader()
Dradv_nir_apply_pipeline_layout.c533 .gfx_level = device->physical_device->rad_info.gfx_level, in radv_nir_apply_pipeline_layout()
534 .address32_hi = device->physical_device->rad_info.address32_hi, in radv_nir_apply_pipeline_layout()
536 .has_image_load_dcc_bug = device->physical_device->rad_info.has_image_load_dcc_bug, in radv_nir_apply_pipeline_layout()
Dradv_meta_buffer.c236 if (device->physical_device->rad_info.gfx_level >= GFX10 && in radv_prefer_compute_dma()
237 device->physical_device->rad_info.has_dedicated_vram) { in radv_prefer_compute_dma()
Dradv_meta_clear.c1265 if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) { in radv_clear_cmask()
1313 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10) { in radv_clear_dcc()
1318 } else if (cmd_buffer->device->physical_device->rad_info.gfx_level == GFX9) { in radv_clear_dcc()
1473 assert(cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10); in radv_clear_htile()
1537 return device->physical_device->rad_info.gfx_level >= GFX11 ? RADV_DCC_GFX11_CLEAR_SINGLE in radv_dcc_single_clear_value()
1750 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) { in radv_can_fast_clear_color()
1760 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) { in radv_can_fast_clear_color()
1820 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) { in radv_fast_clear_color()
Dradv_meta_resolve.c278 if (device->physical_device->rad_info.gfx_level >= GFX9) { in image_hw_resolve_compat()
547 pdevice->rad_info.gfx_level >= GFX11 ? RESOLVE_FRAGMENT : RESOLVE_HW; in radv_CmdResolveImage2()
651 pdevice->rad_info.gfx_level >= GFX11 ? RESOLVE_FRAGMENT : RESOLVE_HW; in radv_cmd_buffer_resolve_subpass()
Dradv_meta_copy.c79 if (device->physical_device->rad_info.gfx_level >= GFX9 && in radv_image_is_renderable()
445 (radv_dcc_formats_compatible(cmd_buffer->device->physical_device->rad_info.gfx_level, in copy_image()
Dradv_spm.c189 const struct radeon_info *info = &device->physical_device->rad_info; in radv_spm_init()
/third_party/mesa3d/src/amd/common/
Dac_rgp.c431 static void ac_sqtt_fill_asic_info(struct radeon_info *rad_info, in ac_sqtt_fill_asic_info() argument
434 bool has_wave32 = rad_info->gfx_level >= GFX10; in ac_sqtt_fill_asic_info()
447 if (rad_info->gfx_level < GFX9) in ac_sqtt_fill_asic_info()
451 if (rad_info->gfx_level >= GFX9) in ac_sqtt_fill_asic_info()
454 chunk->trace_shader_core_clock = rad_info->max_gpu_freq_mhz * 1000000ull; in ac_sqtt_fill_asic_info()
455 chunk->trace_memory_clock = rad_info->memory_freq_mhz * 1000000ull; in ac_sqtt_fill_asic_info()
464 chunk->device_id = rad_info->pci_id; in ac_sqtt_fill_asic_info()
465 chunk->device_revision_id = rad_info->pci_rev_id; in ac_sqtt_fill_asic_info()
466 chunk->vgprs_per_simd = rad_info->num_physical_wave64_vgprs_per_simd * (has_wave32 ? 2 : 1); in ac_sqtt_fill_asic_info()
467 chunk->sgprs_per_simd = rad_info->num_physical_sgprs_per_simd; in ac_sqtt_fill_asic_info()
[all …]
Dac_sqtt.c39 ac_thread_trace_get_data_offset(const struct radeon_info *rad_info, in ac_thread_trace_get_data_offset() argument
42 unsigned max_se = rad_info->max_se; in ac_thread_trace_get_data_offset()
59 ac_thread_trace_get_data_va(const struct radeon_info *rad_info, in ac_thread_trace_get_data_va() argument
62 return va + ac_thread_trace_get_data_offset(rad_info, data, se); in ac_thread_trace_get_data_va()
66 ac_is_thread_trace_complete(struct radeon_info *rad_info, in ac_is_thread_trace_complete() argument
70 if (rad_info->gfx_level >= GFX10) { in ac_is_thread_trace_complete()
90 ac_get_expected_buffer_size(struct radeon_info *rad_info, in ac_get_expected_buffer_size() argument
93 if (rad_info->gfx_level >= GFX10) { in ac_get_expected_buffer_size()
94 uint32_t dropped_cntr_per_se = info->gfx10_dropped_cntr / rad_info->max_se; in ac_get_expected_buffer_size()
Dac_sqtt.h86 ac_thread_trace_get_data_offset(const struct radeon_info *rad_info,
92 ac_thread_trace_get_data_va(const struct radeon_info *rad_info,
96 ac_is_thread_trace_complete(struct radeon_info *rad_info,
101 ac_get_expected_buffer_size(struct radeon_info *rad_info,

12