Home
last modified time | relevance | path

Searched refs:ITM (Results 1 – 15 of 15) sorted by relevance

/third_party/openssl/test/
Dacvp_test.inc12 #define ITM(x) x, sizeof(x)
77 ITM(ecdsa_pv_pub0),
82 ITM(ecdsa_pv_pub1),
109 ITM(ecdsa_siggen_msg0),
217 ITM(ecdsa_sigver_msg0),
218 ITM(ecdsa_sigver_pub0),
219 ITM(ecdsa_sigver_r0),
220 ITM(ecdsa_sigver_s0),
226 ITM(ecdsa_sigver_msg1),
227 ITM(ecdsa_sigver_pub1),
[all …]
/third_party/node/deps/openssl/openssl/providers/fips/
Dself_test_data.inc11 #define ITM(x) ((void *)&x), sizeof(x)
16 { name, OSSL_PARAM_UNSIGNED_INTEGER, ITM(data) }
18 { name, OSSL_PARAM_OCTET_STRING, ITM(data) }
22 { name, OSSL_PARAM_UTF8_STRING, ITM(data) }
24 { name, OSSL_PARAM_INTEGER, ITM(i) }
154 ITM(sha1_digest),
160 ITM(sha512_digest),
165 ITM(sha3_256_pt),
166 ITM(sha3_256_digest),
243 ITM(des_ede3_cbc_pt),
[all …]
/third_party/openssl/providers/fips/
Dself_test_data.inc11 #define ITM(x) ((void *)&x), sizeof(x)
16 { name, OSSL_PARAM_UNSIGNED_INTEGER, ITM(data) }
18 { name, OSSL_PARAM_OCTET_STRING, ITM(data) }
22 { name, OSSL_PARAM_UTF8_STRING, ITM(data) }
24 { name, OSSL_PARAM_INTEGER, ITM(i) }
154 ITM(sha1_digest),
160 ITM(sha512_digest),
165 ITM(sha3_256_pt),
166 ITM(sha3_256_digest),
243 ITM(des_ede3_cbc_pt),
[all …]
/third_party/cmsis/CMSIS/Core/Include/
Dcore_sc300.h1381 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct… macro
1888 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ in ITM_SendChar()
1889 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
1891 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
1895 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
Dcore_cm3.h1398 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct… macro
1914 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ in ITM_SendChar()
1915 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
1917 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
1921 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
Dcore_cm4.h1575 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct… macro
2107 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ in ITM_SendChar()
2108 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
2110 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
2114 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
Dcore_cm7.h1802 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct… macro
2344 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ in ITM_SendChar()
2345 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
2347 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
2351 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
Dcore_armv8mml.h2162 …#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration stru… macro
3169 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ in ITM_SendChar()
3170 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
3172 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
3176 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
Dcore_cm35p.h2237 …#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration stru… macro
3237 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ in ITM_SendChar()
3238 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
3240 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
3244 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
Dcore_cm33.h2237 …#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration stru… macro
3237 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ in ITM_SendChar()
3238 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
3240 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
3244 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
Dcore_starmc1.h2165 …#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration stru… macro
3552 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ in ITM_SendChar()
3553 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
3555 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
3559 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
Dcore_armv81mml.h3132 …#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration stru… macro
4188 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ in ITM_SendChar()
4189 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
4191 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
4195 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
Dcore_cm85.h3583 …#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration stru… macro
4714 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ in ITM_SendChar()
4715 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
4717 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
4721 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
Dcore_cm55.h3679 …#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration stru… macro
4848 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ in ITM_SendChar()
4849 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
4851 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
4855 ITM->PORT[0U].u8 = (uint8_t)ch; in ITM_SendChar()
/third_party/NuttX/
DReleaseNotes7461 - Add ARMv7-M CMSIS ITM header file and library. From Pierre-noel
7465 - Add ARMv7-M support to use ITM for SYSLOG debug output. Includes
21467 - ITM: Fix missing space causing macro issues From Alan Carvalho de
22090 - STM32F7 ITM: Add ITM syslog support. From Valmantas Paliksa.
25497 then make sure that ITM and DWT resources are enabled before
25498 accessing ITM and DWT registers. By default, these registers are