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Searched refs:smem (Results 1 – 25 of 29) sorted by relevance

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/third_party/mesa3d/src/amd/vulkan/radix_sort/shaders/
Dscatter.glsl322 shared rs_scatter_smem smem;
340 #define RS_PREFIX_SWEEP0(idx_) smem.extent[RS_SMEM_PREFIX_OFFSET + RS_SWEEP_0_OFFSET + (idx_)]
345 #define RS_PREFIX_SWEEP1(idx_) smem.extent[RS_SMEM_PREFIX_OFFSET + RS_SWEEP_1_OFFSET + (idx_)]
351 #define RS_PREFIX_SWEEP2(idx_) smem.extent[RS_SMEM_PREFIX_OFFSET + RS_SWEEP_2_OFFSET + (idx_)]
362 #define RS_PREFIX_LOAD(idx_) smem.extent[RS_SMEM_HISTOGRAM_OFFSET + gl_SubgroupInvocationID + (id…
363 #define RS_PREFIX_STORE(idx_) smem.extent[RS_SMEM_HISTOGRAM_OFFSET + gl_SubgroupInvocationID + (id…
365 #define RS_PREFIX_LOAD(idx_) smem.extent[RS_SMEM_HISTOGRAM_OFFSET + gl_LocalInvocationID.x + (idx…
366 #define RS_PREFIX_STORE(idx_) smem.extent[RS_SMEM_HISTOGRAM_OFFSET + gl_LocalInvocationID.x + (idx…
392 smem.extent[smem_offset + ii] = 0;
401 smem.extent[smem_offset + ii] = 0;
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Dhistogram.comp163 shared rs_histogram_smem smem;
205 smem.histogram[smem_offset + ii] = 0;
214 smem.histogram[smem_offset + ii] = 0;
221 smem.histogram[smem_idx] = 0;
230 smem.histogram[gl_LocalInvocationID.x] = 0;
251 const uint32_t count = smem.histogram[smem_offset + ii];
262 const uint32_t count = smem.histogram[smem_offset + ii];
271 const uint32_t count = smem.histogram[smem_idx];
283 const uint32_t count = smem.histogram[gl_LocalInvocationID.x];
381 atomicAdd(smem.histogram[digit], 1); \
/third_party/mesa3d/src/amd/compiler/tests/
Dtest_assembler.cpp37 bld.smem(aco_opcode::s_memtime, bld.def(s2)).def(0).setFixed(PhysReg{0});
277 bld.smem(aco_opcode::s_load_dword, dst, sbase, offset);
280 bld.smem(aco_opcode::s_load_dword, dst, sbase, Operand::c32(0x42));
284 bld.smem(aco_opcode::s_load_dword, dst, sbase, Operand::c32(0x42), offset);
Dtest_hard_clause.cpp87 bld.smem(aco_opcode::s_load_dword, Definition(PhysReg(0), s1), Operand(PhysReg(0), s2), in create_smem()
95 bld.smem(aco_opcode::s_buffer_load_dword, Definition(PhysReg(0), s1), desc_op, Operand::zero()); in create_smem_buffer()
/third_party/mesa3d/src/amd/compiler/
Daco_insert_waitcnt.cpp388 if (ctx.pending_s_buffer_store && !instr->smem().definitions.empty() && in kill()
389 !instr->smem().sync.can_reorder()) { in kill()
658 SMEM_instruction& smem = instr->smem(); in gen() local
659 update_counters(ctx, event_smem, smem.sync); in gen()
663 else if (ctx.gfx_level >= GFX10 && !smem.sync.can_reorder()) in gen()
Daco_print_ir.cpp340 const SMEM_instruction& smem = instr->smem(); in print_instr_format_specific() local
341 if (smem.glc) in print_instr_format_specific()
343 if (smem.dlc) in print_instr_format_specific()
345 if (smem.nv) in print_instr_format_specific()
347 print_sync(smem.sync, output); in print_instr_format_specific()
Daco_assembler.cpp179 SMEM_instruction& smem = instr->smem(); in emit_instruction() local
209 assert(!smem.dlc); /* Device-level coherent is not supported on GFX9 and lower */ in emit_instruction()
210 encoding |= smem.nv ? 1 << 15 : 0; in emit_instruction()
213 assert(!smem.nv); /* Non-volatile is not supported on GFX10 */ in emit_instruction()
214 encoding |= smem.dlc ? 1 << 14 : 0; in emit_instruction()
218 encoding |= smem.glc ? 1 << 16 : 0; in emit_instruction()
Daco_optimizer.cpp814 skip_smem_offset_align(opt_ctx& ctx, SMEM_instruction* smem) in skip_smem_offset_align() argument
816 bool soe = smem->operands.size() >= (!smem->definitions.empty() ? 3 : 4); in skip_smem_offset_align()
817 if (soe && !smem->operands[1].isConstant()) in skip_smem_offset_align()
823 Operand& op = smem->operands[soe ? smem->operands.size() - 1 : 1]; in skip_smem_offset_align()
844 skip_smem_offset_align(ctx, &instr->smem()); in smem_combine()
848 SMEM_instruction& smem = instr->smem(); in smem_combine() local
853 bool prevent_overflow = smem.operands[0].size() > 2 || smem.prevent_overflow; in smem_combine()
862 bool soe = smem.operands.size() >= (!smem.definitions.empty() ? 3 : 4); in smem_combine()
864 if (ctx.info[smem.operands.back().tempId()].is_constant_or_literal(32) && in smem_combine()
865 ctx.info[smem.operands.back().tempId()].val == 0) { in smem_combine()
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Daco_opt_value_numbering.cpp212 SMEM_instruction& aS = a->smem(); in operator ()()
213 SMEM_instruction& bS = b->smem(); in operator ()()
Daco_statistics.cpp134 case instr_class::smem: return {0, WAIT_USE(scalar, 1)}; in get_perf_info()
162 case instr_class::smem: return {4, WAIT_USE(scalar, 4)}; in get_perf_info()
Daco_ir.h121 smem = 11, enumerator
1105 SMEM_instruction& smem() noexcept in smem() function
1110 const SMEM_instruction& smem() const noexcept in smem() function
Daco_instruction_selection.cpp4955 split_buffer_store(isel_context* ctx, nir_intrinsic_instr* instr, bool smem, RegType dst_type, in split_buffer_store() argument
4983 if ((ctx->program->gfx_level == GFX6 || smem) && byte == 12) in split_buffer_store()
5514 Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, off); in visit_load_input()
5902 bld.smem(op, Definition(vec), ptr, index).instr->smem().prevent_overflow = true; in visit_load_push_constant()
7278 bld.smem(opcode, bld.def(RegType::sgpr, size), base, offset), Operand::c32(0u)); in visit_load_smem()
7280 bld.smem(opcode, Definition(dst), base, offset); in visit_load_smem()
7580 bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand::zero()); in get_scratch_resource()
7705 bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, in visit_emit_vertex_with_counter()
8309 bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, off); in visit_intrinsic()
8494 bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), addr, Operand::zero()), in visit_intrinsic()
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Daco_ir.cpp190 case Format::SMEM: return instr->smem().sync; in get_sync_info()
Daco_spill.cpp1421 bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, Operand::zero()); in load_scratch_resource()
Daco_lower_to_hw_instr.cpp2339 bld.smem(aco_opcode::s_load_dwordx2, instr->definitions[0], scratch_addr, in lower_to_hw_instr()
/third_party/mesa3d/src/panfrost/lib/genxml/
Ddecode.c268 struct pandecode_mapped_memory *smem = in pandecode_sample_locations() local
271 const u16 *PANDECODE_PTR_VAR(samples, smem, params.sample_locations); in pandecode_sample_locations()
849 … struct pandecode_mapped_memory *smem = pandecode_find_mapped_gpu_mem_containing(p->state); in pandecode_dcd() local
850 uint32_t *cl = pandecode_fetch_gpu_mem(smem, p->state, pan_size(RENDERER_STATE)); in pandecode_dcd()
/third_party/mesa3d/docs/relnotes/
D21.1.6.rst110 - nv50/ir/nir: fix smem size for GL
D13.0.4.rst117 - radv: flush smem for uniform buffer bit.
D22.1.0.rst3088 - aco: don't expand smem/mubuf global loads
D20.1.0.rst3545 - aco: add vmem/smem score statistic
D21.3.0.rst2325 - nv50/ir/nir: fix smem size for GL
D20.3.0.rst3081 - nv50/ir/nir: fix smem size
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_clear.c604 const uint32_t smem = 0; in si_get_htile_clear_value() local
641 ((smem & 0x3) << 8) | in si_get_htile_clear_value()
/third_party/mesa3d/src/amd/vulkan/
Dradv_meta_clear.c732 uint32_t zmask = 0, smem = 0; in radv_get_htile_fast_clear_value() local
771 ((smem & 0x3) << 8) | in radv_get_htile_fast_clear_value()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPU.td175 def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",

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