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Searched refs:sscreen (Results 1 – 25 of 46) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_pipe.c139 bool si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler) in si_init_compiler() argument
144 !sscreen->info.has_dedicated_vram && sscreen->info.gfx_level <= GFX8; in si_init_compiler()
147 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) | in si_init_compiler()
152 if (!ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options)) in si_init_compiler()
162 void si_init_aux_async_compute_ctx(struct si_screen *sscreen) in si_init_aux_async_compute_ctx() argument
164 assert(!sscreen->async_compute_context); in si_init_aux_async_compute_ctx()
165 sscreen->async_compute_context = si_create_context( in si_init_aux_async_compute_ctx()
166 &sscreen->b, in si_init_aux_async_compute_ctx()
168 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) | in si_init_aux_async_compute_ctx()
172 if (sscreen->async_compute_context) in si_init_aux_async_compute_ctx()
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Dsi_get.c49 struct si_screen *sscreen = (struct si_screen *)pscreen; in si_get_param() local
52 bool enable_sparse = sscreen->info.gfx_level >= GFX9 && in si_get_param()
53 sscreen->info.has_sparse_vm_mappings; in si_get_param()
177 return !(sscreen->debug_flags & DBG(NO_FAST_DISPLAY_LIST)); in si_get_param()
180 return sscreen->info.gfx_level < GFX11; in si_get_param()
189 return sscreen->info.has_3d_cube_border_color_mipmap; in si_get_param()
192 return sscreen->info.gfx_level >= GFX10; in si_get_param()
195 return sscreen->info.has_graphics; in si_get_param()
198 return !SI_BIG_ENDIAN && sscreen->info.has_userptr; in si_get_param()
201 return sscreen->info.has_tmz_support; in si_get_param()
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Dsi_gpu_load.c80 static void si_update_mmio_counters(struct si_screen *sscreen, union si_mmio_counters *counters) in si_update_mmio_counters() argument
86 sscreen->ws->read_registers(sscreen->ws, GRBM_STATUS, 1, &value); in si_update_mmio_counters()
104 if (sscreen->info.gfx_level == GFX7 || sscreen->info.gfx_level == GFX8) { in si_update_mmio_counters()
106 sscreen->ws->read_registers(sscreen->ws, SRBM_STATUS2, 1, &value); in si_update_mmio_counters()
112 if (sscreen->info.gfx_level >= GFX8) { in si_update_mmio_counters()
114 sscreen->ws->read_registers(sscreen->ws, CP_STAT, 1, &value); in si_update_mmio_counters()
132 struct si_screen *sscreen = (struct si_screen *)param; in si_gpu_load_thread() local
137 while (!p_atomic_read(&sscreen->gpu_load_stop_thread)) { in si_gpu_load_thread()
154 si_update_mmio_counters(sscreen, &sscreen->mmio_counters); in si_gpu_load_thread()
156 p_atomic_dec(&sscreen->gpu_load_stop_thread); in si_gpu_load_thread()
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Dsi_texture.c45 static enum radeon_surf_mode si_choose_tiling(struct si_screen *sscreen,
131 static unsigned si_texture_get_offset(struct si_screen *sscreen, struct si_texture *tex, in si_texture_get_offset() argument
135 if (sscreen->info.gfx_level >= GFX9) { in si_texture_get_offset()
173 static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surface, in si_init_surface() argument
197 if ((sscreen->debug_flags & DBG(NO_HYPERZ)) || in si_init_surface()
201 (sscreen->info.gfx_level >= GFX9 || array_mode == RADEON_SURF_MODE_2D)) { in si_init_surface()
207 if (sscreen->info.gfx_level == GFX8) in si_init_surface()
218 if (sscreen->info.gfx_level >= GFX8 && modifier == DRM_FORMAT_MOD_INVALID && !is_imported) { in si_init_surface()
223 if (ptex->nr_samples >= 2 && sscreen->debug_flags & DBG(NO_DCC_MSAA)) in si_init_surface()
230 (sscreen->debug_flags & DBG(NO_DCC) || in si_init_surface()
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Dsi_shader_nir.c31 struct si_screen *sscreen = (struct si_screen *)data; in si_alu_to_scalar_filter() local
33 if (sscreen->info.has_packed_math_16bit && instr->type == nir_instr_type_alu) { in si_alu_to_scalar_filter()
57 void si_nir_opts(struct si_screen *sscreen, struct nir_shader *nir, bool first) in si_nir_opts() argument
67 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, si_alu_to_scalar_filter, sscreen); in si_nir_opts()
90 NIR_PASS_V(nir, nir_lower_alu_to_scalar, si_alu_to_scalar_filter, sscreen); in si_nir_opts()
130 if (sscreen->info.has_packed_math_16bit) in si_nir_opts()
158 static void si_late_optimize_16bit_samplers(struct si_screen *sscreen, nir_shader *nir) in si_late_optimize_16bit_samplers() argument
175 bool has_g16 = sscreen->info.gfx_level >= GFX10 && LLVM_VERSION_MAJOR >= 12; in si_late_optimize_16bit_samplers()
201 si_nir_opts(sscreen, nir, false); in si_late_optimize_16bit_samplers()
240 static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir) in si_lower_nir() argument
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Dsi_buffer.c45 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size, in si_init_resource_fields() argument
59 if (sscreen->info.smart_access_memory) in si_init_resource_fields()
92 if (!sscreen->info.is_amdgpu) in si_init_resource_fields()
111 (sscreen->debug_flags & DBG(TMZ) && in si_init_resource_fields()
118 if (sscreen->debug_flags & DBG(NO_WC)) in si_init_resource_fields()
137 if (sscreen->info.gfx_level >= GFX9 && in si_init_resource_fields()
142 sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 47) { in si_init_resource_fields()
149 sscreen->options.mall_noalloc) in si_init_resource_fields()
160 if (!sscreen->info.smart_access_memory && in si_init_resource_fields()
161 sscreen->info.has_dedicated_vram && in si_init_resource_fields()
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Dsi_state_shaders.cpp40 unsigned si_determine_wave_size(struct si_screen *sscreen, struct si_shader *shader) in si_determine_wave_size() argument
46 if (sscreen->info.gfx_level < GFX10) in si_determine_wave_size()
65 if (sscreen->debug_flags & in si_determine_wave_size()
70 if (sscreen->debug_flags & in si_determine_wave_size()
100 LLVM_VERSION_MAJOR == 13 && !(sscreen->debug_flags & DBG(W32_PS_DISCARD))) in si_determine_wave_size()
121 !(sscreen->info.gfx_level == GFX10 && shader && shader->key.ge.opt.ngg_culling)) in si_determine_wave_size()
349 void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20], in si_shader_cache_insert_shader() argument
355 bool memory_cache_full = sscreen->shader_cache_size >= sscreen->shader_cache_max_size; in si_shader_cache_insert_shader()
360 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key); in si_shader_cache_insert_shader()
394 if (_mesa_hash_table_insert(sscreen->shader_cache, in si_shader_cache_insert_shader()
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Dradeon_vce.c219 struct si_screen *sscreen = (struct si_screen *)enc->screen; in si_vce_frame_offset() local
222 if (sscreen->info.gfx_level < GFX9) { in si_vce_frame_offset()
385 struct si_screen *sscreen = (struct si_screen *)context->screen; in si_vce_create_encoder() local
392 if (!sscreen->info.vce_fw_version) { in si_vce_create_encoder()
396 } else if (!si_vce_is_fw_version_supported(sscreen)) { in si_vce_create_encoder()
405 if (sscreen->info.is_amdgpu) in si_vce_create_encoder()
410 if (sscreen->info.family >= CHIP_TONGA && sscreen->info.family != CHIP_STONEY && in si_vce_create_encoder()
411 sscreen->info.family != CHIP_POLARIS11 && sscreen->info.family != CHIP_POLARIS12 && in si_vce_create_encoder()
412 sscreen->info.family != CHIP_VEGAM) in si_vce_create_encoder()
415 if ((sscreen->info.family >= CHIP_TONGA) && (templ->max_references == 1) && in si_vce_create_encoder()
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Dsi_compute.c36 #define COMPUTE_DBG(sscreen, fmt, args...) \ argument
38 if ((sscreen->debug_flags & DBG(COMPUTE))) \
117 struct si_screen *sscreen = sel->screen; in si_create_compute_state_async() local
121 assert(thread_index < ARRAY_SIZE(sscreen->compiler)); in si_create_compute_state_async()
122 compiler = &sscreen->compiler[thread_index]; in si_create_compute_state_async()
125 si_init_compiler(sscreen, compiler); in si_create_compute_state_async()
128 si_nir_scan_shader(sscreen, sel->nir, &sel->info); in si_create_compute_state_async()
130 si_get_active_slot_masks(sscreen, &sel->info, &sel->active_const_and_shader_buffers, in si_create_compute_state_async()
158 if (sscreen->info.gfx_level < GFX11) in si_create_compute_state_async()
180 simple_mtx_lock(&sscreen->shader_cache_mutex); in si_create_compute_state_async()
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Dsi_shader.c915 bool si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader, in si_shader_binary_upload() argument
919 if (!si_shader_binary_open(sscreen, shader, &binary)) in si_shader_binary_upload()
924 &sscreen->b, in si_shader_binary_upload()
925 (sscreen->info.cpdma_prefetch_writes_memory ? 0 : SI_RESOURCE_FLAG_READ_ONLY) | in si_shader_binary_upload()
937 u.rx_ptr = sscreen->ws->buffer_map(sscreen->ws, in si_shader_binary_upload()
945 if (sscreen->debug_flags & DBG(SQTT)) { in si_shader_binary_upload()
952 sscreen->ws->buffer_unmap(sscreen->ws, shader->bo->buf); in si_shader_binary_upload()
1020 struct si_screen *sscreen = shader->selector->screen; in si_calculate_max_simd_waves() local
1023 unsigned lds_increment = get_lds_granularity(sscreen, shader->selector->stage); in si_calculate_max_simd_waves()
1027 max_simd_waves = sscreen->info.max_wave64_per_simd; in si_calculate_max_simd_waves()
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Dsi_query.c517 void si_query_buffer_destroy(struct si_screen *sscreen, struct si_query_buffer *buffer) in si_query_buffer_destroy() argument
640 static unsigned si_query_pipestats_num_results(struct si_screen *sscreen) in si_query_pipestats_num_results() argument
642 return sscreen->info.gfx_level >= GFX11 ? 14 : 11; in si_query_pipestats_num_results()
668 unsigned si_query_pipestat_end_dw_offset(struct si_screen *sscreen, in si_query_pipestat_end_dw_offset() argument
671 return si_query_pipestats_num_results(sscreen) * 2 + si_query_pipestat_dw_offset(index); in si_query_pipestat_end_dw_offset()
684 static void si_query_hw_add_result(struct si_screen *sscreen, struct si_query_hw *, void *buffer,
696 static struct pipe_query *si_query_hw_create(struct si_screen *sscreen, unsigned query_type, in si_query_hw_create() argument
711 query->result_size = 16 * sscreen->info.max_render_backends; in si_query_hw_create()
713 query->b.num_cs_dw_suspend = 6 + si_cp_write_fence_dwords(sscreen); in si_query_hw_create()
717 query->b.num_cs_dw_suspend = 8 + si_cp_write_fence_dwords(sscreen); in si_query_hw_create()
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Dsi_state_binning.c43 static struct uvec2 si_find_bin_size(struct si_screen *sscreen, const si_bin_size_subtable table[], in si_find_bin_size() argument
47 util_logbase2_ceil(sscreen->info.max_render_backends / sscreen->info.max_se); in si_find_bin_size()
48 unsigned log_num_se = util_logbase2_ceil(sscreen->info.max_se); in si_find_bin_size()
444 struct si_screen *sscreen = sctx->screen; in si_emit_dpbb_state() local
451 if (!sscreen->dpbb_allowed || sctx->dpbb_force_off || in si_emit_dpbb_state()
466 if (sscreen->info.max_render_backends > 4 && ps_can_kill && db_can_reject_z_trivially && in si_emit_dpbb_state()
515 S_028C44_CONTEXT_STATES_PER_BIN(sscreen->pbb_context_states_per_bin - 1) | in si_emit_dpbb_state()
516 S_028C44_PERSISTENT_STATES_PER_BIN(sscreen->pbb_persistent_states_per_bin - 1) | in si_emit_dpbb_state()
Dsi_pipe.h1349 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size,
1351 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res);
1363 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1381 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1423 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst, uint64_t offset,
1490 void si_init_screen_get_functions(struct si_screen *sscreen);
1511 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1512 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1513 unsigned si_end_counter(struct si_screen *sscreen, unsigned type, uint64_t begin);
1520 bool si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler);
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Dsi_state.c400 static void si_blend_check_commutativity(struct si_screen *sscreen, struct si_state_blend *blend, in si_blend_check_commutativity() argument
932 struct si_screen *sscreen = ((struct si_context *)ctx)->screen; in si_create_rs_state() local
1052 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.gfx_level >= GFX9)); in si_create_rs_state()
1070 S_028814_KEEP_TOGETHER_ENABLE(sscreen->info.gfx_level >= GFX10 ? in si_create_rs_state()
1823 struct si_screen *sscreen = (struct si_screen *)screen; in si_translate_texformat() local
1827 assert(sscreen->info.gfx_level <= GFX9); in si_translate_texformat()
1843 if (sscreen->info.gfx_level <= GFX8) in si_translate_texformat()
1897 (sscreen->info.family == CHIP_STONEY || sscreen->info.family == CHIP_VEGA10 || in si_translate_texformat()
1898 sscreen->info.family == CHIP_RAVEN || sscreen->info.family == CHIP_RAVEN2)) { in si_translate_texformat()
2164 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex, unsigned view_target, in si_tex_dim() argument
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Dsi_state.h487 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture *tex,
536 void si_init_screen_state_functions(struct si_screen *sscreen);
548 unsigned gfx103_get_cu_mask_ps(struct si_screen *sscreen);
567 bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
569 void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
572 void si_init_screen_live_shader_cache(struct si_screen *sscreen);
574 bool si_init_shader_cache(struct si_screen *sscreen);
575 void si_destroy_shader_cache(struct si_screen *sscreen);
580 void si_get_active_slot_masks(struct si_screen *sscreen, const struct si_shader_info *info,
606 void si_set_vertex_buffer_descriptor(struct si_screen *sscreen, struct si_vertex_elements *velems,
Dsi_fence.c91 struct si_screen *sscreen = ctx->screen; in si_cp_release_mem() local
100 si_aligned_buffer_create(&sscreen->b, in si_cp_release_mem()
105 16 * sscreen->info.max_render_backends, 256); in si_cp_release_mem()
384 struct si_screen *sscreen = (struct si_screen *)ctx->screen; in si_create_fence_fd() local
385 struct radeon_winsys *ws = sscreen->ws; in si_create_fence_fd()
396 if (!sscreen->info.has_fence_to_handle) in si_create_fence_fd()
403 if (!sscreen->info.has_syncobj) in si_create_fence_fd()
424 struct si_screen *sscreen = (struct si_screen *)screen; in si_fence_get_fd() local
425 struct radeon_winsys *ws = sscreen->ws; in si_fence_get_fd()
429 if (!sscreen->info.has_fence_to_handle) in si_fence_get_fd()
Dsi_test_image_copy_region.c223 static enum pipe_format get_random_format(struct si_screen *sscreen, bool render_target, in get_random_format() argument
323 if (sscreen->b.is_format_supported(&sscreen->b, format, PIPE_TEXTURE_2D, 1, 1, bind)) in get_random_format()
432 static void print_image_attrs(struct si_screen *sscreen, struct si_texture *tex) in print_image_attrs() argument
436 if (sscreen->info.gfx_level >= GFX9) { in print_image_attrs()
483 void si_test_image_copy_region(struct si_screen *sscreen) in si_test_image_copy_region() argument
485 struct pipe_screen *screen = &sscreen->b; in si_test_image_copy_region()
523 tsrc.format = tdst.format = get_random_format(sscreen, false, 0, 0, 0, &format_options); in si_test_image_copy_region()
542 print_image_attrs(sscreen, sdst); in si_test_image_copy_region()
544 print_image_attrs(sscreen, ssrc); in si_test_image_copy_region()
643 void si_test_blit(struct si_screen *sscreen, unsigned test_flags) in si_test_blit() argument
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Dsi_shader.h968 bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
970 bool si_create_shader_variant(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
975 bool si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader,
977 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
981 void si_multiwave_lds_size_workaround(struct si_screen *sscreen, unsigned *lds_size);
988 void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
992 struct si_shader *si_generate_gs_copy_shader(struct si_screen *sscreen,
999 void si_nir_opts(struct si_screen *sscreen, struct nir_shader *nir, bool first);
1004 unsigned si_determine_wave_size(struct si_screen *sscreen, struct si_shader *shader);
Dsi_clear.c107 static bool si_alloc_separate_cmask(struct si_screen *sscreen, struct si_texture *tex) in si_alloc_separate_cmask() argument
109 assert(sscreen->info.gfx_level < GFX11); in si_alloc_separate_cmask()
121 si_aligned_buffer_create(&sscreen->b, PIPE_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT, in si_alloc_separate_cmask()
129 p_atomic_inc(&sscreen->compressed_colortex_counter); in si_alloc_separate_cmask()
170 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format) in vi_alpha_is_on_msb() argument
174 unsigned comp_swap = si_translate_colorswap(sscreen->info.gfx_level, format, false); in vi_alpha_is_on_msb()
178 return (comp_swap == V_028C70_SWAP_ALT_REV) != (sscreen->info.family == CHIP_RAVEN2 || in vi_alpha_is_on_msb()
179 sscreen->info.family == CHIP_RENOIR); in vi_alpha_is_on_msb()
185 static bool gfx8_get_dcc_clear_parameters(struct si_screen *sscreen, enum pipe_format base_format, in gfx8_get_dcc_clear_parameters() argument
214 bool base_alpha_is_on_msb = vi_alpha_is_on_msb(sscreen, base_format); in gfx8_get_dcc_clear_parameters()
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Dsi_shader_llvm_gs.c383 struct si_shader *si_generate_gs_copy_shader(struct si_screen *sscreen, in si_generate_gs_copy_shader() argument
406 shader->wave_size = si_determine_wave_size(sscreen, shader); in si_generate_gs_copy_shader()
427 si_llvm_context_init(&ctx, sscreen, compiler, shader->wave_size); in si_generate_gs_copy_shader()
447 if (!sscreen->use_ngg_streamout && ctx.so.num_outputs) in si_generate_gs_copy_shader()
499 if (!sscreen->use_ngg_streamout && ctx.so.num_outputs) { in si_generate_gs_copy_shader()
517 if (si_compile_llvm(sscreen, &ctx.shader->binary, &ctx.shader->config, ctx.compiler, &ctx.ac, in si_generate_gs_copy_shader()
521 ok = si_shader_binary_upload(sscreen, ctx.shader, 0); in si_generate_gs_copy_shader()
523 if (si_can_dump_shader(sscreen, MESA_SHADER_GEOMETRY)) in si_generate_gs_copy_shader()
525 si_shader_dump(sscreen, ctx.shader, debug, stderr, true); in si_generate_gs_copy_shader()
534 si_fix_resource_usage(sscreen, shader); in si_generate_gs_copy_shader()
Dsi_state_draw.cpp884 static unsigned si_get_init_multi_vgt_param(struct si_screen *sscreen, union si_vgt_param_key *key) in si_get_init_multi_vgt_param() argument
902 if ((sscreen->info.family == CHIP_TAHITI || sscreen->info.family == CHIP_PITCAIRN || in si_get_init_multi_vgt_param()
903 sscreen->info.family == CHIP_BONAIRE) && in si_get_init_multi_vgt_param()
908 if (sscreen->info.has_distributed_tess) { in si_get_init_multi_vgt_param()
910 if (sscreen->info.gfx_level == GFX8) in si_get_init_multi_vgt_param()
919 if (key->u.line_stipple_enabled || (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) { in si_get_init_multi_vgt_param()
924 if (sscreen->info.gfx_level >= GFX7) { in si_get_init_multi_vgt_param()
932 if (sscreen->info.max_se <= 2 || key->u.prim == PIPE_PRIM_POLYGON || in si_get_init_multi_vgt_param()
936 (sscreen->info.family < CHIP_POLARIS10 || in si_get_init_multi_vgt_param()
945 if (sscreen->info.family == CHIP_HAWAII && key->u.uses_instancing) in si_get_init_multi_vgt_param()
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Dsi_shader_internal.h178 void si_fix_resource_usage(struct si_screen *sscreen, struct si_shader *shader);
195 bool si_compile_llvm(struct si_screen *sscreen, struct si_shader_binary *binary,
199 void si_llvm_context_init(struct si_shader_context *ctx, struct si_screen *sscreen,
225 bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
Dradeon_uvd_enc.c268 struct si_screen *sscreen = (struct si_screen *)context->screen; in radeon_uvd_create_encoder() local
275 if (!si_radeon_uvd_enc_supported(sscreen)) { in radeon_uvd_create_encoder()
324 cpb_size = (sscreen->info.gfx_level < GFX9) in radeon_uvd_create_encoder()
352 bool si_radeon_uvd_enc_supported(struct si_screen *sscreen) in si_radeon_uvd_enc_supported() argument
354 return sscreen->info.ip[AMD_IP_UVD_ENC].num_queues; in si_radeon_uvd_enc_supported()
Dsi_shader_llvm.c71 bool si_compile_llvm(struct si_screen *sscreen, struct si_shader_binary *binary, in si_compile_llvm() argument
76 unsigned count = p_atomic_inc_return(&sscreen->num_compilations); in si_compile_llvm()
78 if (si_can_dump_shader(sscreen, stage)) { in si_compile_llvm()
81 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) { in si_compile_llvm()
88 if (sscreen->record_llvm_ir) { in si_compile_llvm()
115 .info = &sscreen->info, in si_compile_llvm()
123 bool ok = ac_rtld_read_config(&sscreen->info, &rtld, conf); in si_compile_llvm()
128 void si_llvm_context_init(struct si_shader_context *ctx, struct si_screen *sscreen, in si_llvm_context_init() argument
132 ctx->screen = sscreen; in si_llvm_context_init()
135 ac_llvm_context_init(&ctx->ac, compiler, sscreen->info.gfx_level, sscreen->info.family, in si_llvm_context_init()
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Dsi_gfx_cs.c38 struct si_screen *sscreen = ctx->screen; in si_flush_gfx_cs() local
55 if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 39) in si_flush_gfx_cs()
88 if (sscreen->debug_flags & DBG(CHECK_VM)) in si_flush_gfx_cs()
106 if (sscreen->use_ngg_streamout) in si_flush_gfx_cs()
144 if (sscreen->debug_flags & DBG(IB)) in si_flush_gfx_cs()
160 if (sscreen->debug_flags & DBG(CHECK_VM)) { in si_flush_gfx_cs()
619 struct si_screen *sscreen = ctx->screen; in si_get_wait_mem_scratch_bo() local
626 assert(sscreen->info.has_tmz_support); in si_get_wait_mem_scratch_bo()
629 si_aligned_buffer_create(&sscreen->b, in si_get_wait_mem_scratch_bo()
634 sscreen->info.tcc_cache_line_size); in si_get_wait_mem_scratch_bo()

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