| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_vec4.h | 154 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
160 bool is_supported_64bit_region(vec4_instruction *inst, unsigned arg);
165 vec4_instruction *inst, int arg);
167 vec4_instruction *emit(vec4_instruction *inst);
169 vec4_instruction *emit(enum opcode opcode);
170 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
171 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
173 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
175 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
179 vec4_instruction *emit_before(bblock_t *block,
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| D | brw_vec4_visitor.cpp | 31 vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst, in vec4_instruction() function in brw::vec4_instruction
65 vec4_instruction *
66 vec4_visitor::emit(vec4_instruction *inst) in emit()
76 vec4_instruction *
77 vec4_visitor::emit_before(bblock_t *block, vec4_instruction *inst, in emit_before()
78 vec4_instruction *new_inst) in emit_before()
88 vec4_instruction *
92 return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0, src1, src2)); in emit()
96 vec4_instruction *
100 return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0, src1)); in emit()
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| D | brw_ir_vec4.h | 269 class vec4_instruction : public backend_instruction {
271 DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
273 vec4_instruction(enum opcode opcode,
371 inline vec4_instruction *
373 vec4_instruction *inst) in set_predicate_inv()
383 inline vec4_instruction *
384 set_predicate(enum brw_predicate pred, vec4_instruction *inst) in set_predicate()
393 inline vec4_instruction *
394 set_condmod(enum brw_conditional_mod mod, vec4_instruction *inst) in set_condmod()
404 inline vec4_instruction *
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| D | brw_vec4_cse.cpp | 41 vec4_instruction *generator;
49 is_expression(const vec4_instruction *const inst) in is_expression()
98 operands_match(const vec4_instruction *a, const vec4_instruction *b) in operands_match()
143 instructions_match(vec4_instruction *a, vec4_instruction *b) in instructions_match()
174 foreach_inst_in_block (vec4_instruction, inst, block) { in opt_cse_local()
218 vec4_instruction *copy = in opt_cse_local()
239 vec4_instruction *copy = in opt_cse_local()
253 vec4_instruction *prev = (vec4_instruction *)inst->prev; in opt_cse_local()
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| D | brw_vec4.cpp | 150 vec4_instruction::is_send_from_grf() const in is_send_from_grf()
187 vec4_instruction::has_source_and_destination_hazard() const in has_source_and_destination_hazard()
206 vec4_instruction::size_read(unsigned arg) const in size_read()
237 vec4_instruction::can_do_source_mods(const struct intel_device_info *devinfo) in can_do_source_mods()
252 vec4_instruction::can_do_cmod() in can_do_cmod()
272 vec4_instruction::can_do_writemask(const struct intel_device_info *devinfo) in can_do_writemask()
308 vec4_instruction::can_change_types() const in can_change_types()
327 vec4_instruction::implied_mrf_writes() const in implied_mrf_writes()
405 vec4_instruction *imm_inst[4]; in opt_vector_float()
409 foreach_inst_in_block_safe(vec4_instruction, inst, block) { in opt_vector_float()
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| D | brw_vec4_reg_allocate.cpp | 55 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in reg_allocate_trivial()
75 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in reg_allocate_trivial()
192 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in reg_allocate()
232 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in reg_allocate()
266 can_use_scratch_for_source(const vec4_instruction *inst, unsigned i, in can_use_scratch_for_source()
279 for (vec4_instruction *prev_inst = (vec4_instruction *) inst->prev; in can_use_scratch_for_source()
281 prev_inst = (vec4_instruction *) prev_inst->prev) { in can_use_scratch_for_source()
362 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in evaluate_spill_costs()
477 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in spill_reg()
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| D | test_vec4_register_coalesce.cpp | 85 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */) in emit_urb_write_opcode()
148 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f))); in TEST_F()
172 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f))); in TEST_F()
195 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2)); in TEST_F()
213 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2)); in TEST_F()
239 vec4_instruction *mul = v->emit(v->MUL(temp, some_src_1, some_src_2)); in TEST_F()
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| D | brw_vec4_vs_visitor.cpp | 46 vec4_instruction *
49 vec4_instruction *inst = emit(VEC4_VS_OPCODE_URB_WRITE); in emit_urb_write_opcode()
72 vec4_instruction *inst = emit_generic_urb_slot(reg, varying, 0); in emit_urb_slot()
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| D | test_vec4_dead_code_eliminate.cpp | 82 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */) in emit_urb_write_opcode()
150 vec4_instruction *test_cmp = in TEST_F()
156 vec4_instruction *test_mov = in TEST_F()
162 vec4_instruction *test_sel = in TEST_F()
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| D | brw_vec4_tes.cpp | 61 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in setup_payload()
103 vec4_instruction *
106 vec4_instruction *inst = emit(VEC4_VS_OPCODE_URB_WRITE); in emit_urb_write_opcode()
192 vec4_instruction *read = in nir_emit_intrinsic()
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| D | brw_vec4_cmod_propagation.cpp | 39 writemasks_incompatible(const vec4_instruction *earlier, in writemasks_incompatible()
40 const vec4_instruction *later) in writemasks_incompatible()
55 foreach_inst_in_block_reverse_safe(vec4_instruction, inst, block) { in opt_cmod_propagation_local()
85 foreach_inst_in_block_reverse_starting_from(vec4_instruction, scan_inst, inst) { in opt_cmod_propagation_local()
191 vec4_instruction *mov = v->MOV(scan_inst->dst, temp); in opt_cmod_propagation_local()
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| D | gfx6_gs_visitor.cpp | 75 vec4_instruction *inst = emit(MOV(dst_reg(MRF, 1), in emit_prolog()
168 vec4_instruction *inst = emit(MOV(dst, src_reg(tmp))); in gs_emit_vertex()
224 vec4_instruction *inst = emit(CMP(dst_null_ud(), in gs_end_primitive()
292 vec4_instruction *inst = NULL; in emit_snb_gs_urb_write_opcode()
354 vec4_instruction *inst = NULL; in emit_thread_end()
574 vec4_instruction *inst = emit(MOV(dst_reg(destination_indices), in xfb_write()
628 vec4_instruction *inst = emit(GS_OPCODE_SVB_SET_DST_INDEX, in xfb_program()
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| D | brw_vec4_gs_visitor.cpp | 101 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in setup_varying_inputs()
169 vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, brw_imm_ud(0u)); in emit_prolog()
221 vec4_instruction *inst = emit(MOV(mrf_reg, r0)); in emit_thread_end()
244 vec4_instruction *inst = emit(MOV(mrf_reg, r0)); in emit_urb_write_header()
251 vec4_instruction *
260 vec4_instruction *inst = emit(VEC4_GS_OPCODE_URB_WRITE); in emit_urb_write_opcode()
335 vec4_instruction *inst = emit(MOV(mrf_reg, r0)); in emit_control_data_bits()
464 vec4_instruction *inst = in gs_emit_vertex()
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| D | brw_vec4_copy_propagation.cpp | 44 is_direct_copy(vec4_instruction *inst) in is_direct_copy()
58 is_dominated_by_previous_instruction(vec4_instruction *inst) in is_dominated_by_previous_instruction()
67 is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch) in is_channel_updated()
126 try_constant_propagate(vec4_instruction *inst, in try_constant_propagate()
303 vec4_instruction *inst, int arg, in try_copy_propagate()
472 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in opt_copy_propagation()
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| D | test_vec4_copy_propagation.cpp | 82 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */) in emit_urb_write_opcode()
148 vec4_instruction *test_mov = in TEST_F()
177 vec4_instruction *test_mov = in TEST_F()
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| D | brw_vec4_generator.cpp | 33 vec4_instruction *inst, in generate_math1_gfx4()
56 vec4_instruction *inst, in generate_math_gfx6()
75 vec4_instruction *inst, in generate_math2_gfx4()
111 vec4_instruction *inst, in generate_tex()
338 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst) in generate_vs_urb_write()
352 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst) in generate_gs_urb_write()
367 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst) in generate_gs_urb_write_allocate()
392 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst) in generate_gs_thread_end()
481 vec4_instruction *inst, in generate_gs_svb_write()
523 vec4_instruction *inst, in generate_gs_svb_set_destination_index()
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| D | brw_vec4_tcs.cpp | 99 vec4_instruction *inst; in emit_thread_end()
158 vec4_instruction *inst; in emit_input_urb_read()
193 vec4_instruction *inst; in emit_output_urb_read()
201 vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header)); in emit_output_urb_read()
224 vec4_instruction *inst; in emit_urb_write()
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| D | brw_vec4_tes.h | 57 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
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| D | brw_vec4_vs.h | 48 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
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| D | test_vec4_cmod_propagation.cpp | 92 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */) in emit_urb_write_opcode()
125 static vec4_instruction *
128 vec4_instruction *inst = (vec4_instruction *)block->start(); in instruction()
130 inst = (vec4_instruction *)inst->next; in instruction()
846 vec4_instruction *inst = bld.CMP(dest_null, src0, src1, BRW_CONDITIONAL_GE); in TEST_F()
881 vec4_instruction *inst = bld.CMP(dest_null, src0, src1, BRW_CONDITIONAL_GE); in TEST_F()
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| D | brw_vec4_nir.cpp | 102 vec4_instruction *inst = emit(MOV(dst_null_d(), condition)); in nir_emit_if()
435 vec4_instruction *inst = new(mem_ctx) in nir_emit_intrinsic()
436 vec4_instruction(SHADER_OPCODE_GET_BUFFER_SIZE, result_dst); in nir_emit_intrinsic()
718 vec4_instruction *fence = in nir_emit_intrinsic()
833 vec4_instruction *inst; in emit_find_msb_using_lzd()
1114 vec4_instruction *inst; in nir_emit_alu()
1567 vec4_instruction *inst = emit(MOV(dst_null_df(), value)); in nir_emit_alu()
2123 vec4_instruction *inst = new(mem_ctx) vec4_instruction(opcode, dest); in nir_emit_texture()
2294 vec4_instruction *inst = in emit_mcs_fetch()
2295 new(mem_ctx) vec4_instruction(SHADER_OPCODE_TXF_MCS, in emit_mcs_fetch()
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| D | brw_vec4_gs_visitor.h | 59 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
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| D | brw_vec4_tcs.h | 74 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */) { return NULL; } in emit_urb_write_opcode()
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| D | brw_vec4_live_variables.cpp | 75 foreach_inst_in_block(vec4_instruction, inst, block) { in setup_def_use()
277 foreach_block_and_inst(block, vec4_instruction, inst, s->cfg) { in validate()
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| D | brw_vec4_dead_code_eliminate.cpp | 55 foreach_inst_in_block_reverse_safe(vec4_instruction, inst, block) { in dead_code_eliminate()
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