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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/
Didt,32434-gpio.yaml54 reg = <0x50004 0x10>, <0x38030 0x0c>;
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/
Da6xx_hfi.c34 return 0; in a6xx_hfi_queue_read()
52 for (i = 0; i < HFI_HEADER_SIZE(hdr); i++) { in a6xx_hfi_queue_read()
82 for (i = 0; i < dwords; i++) { in a6xx_hfi_queue_write()
90 queue->data[index] = 0xfafafafa; in a6xx_hfi_queue_write()
96 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
97 return 0; in a6xx_hfi_queue_write()
165 return 0; in a6xx_hfi_wait_for_ack()
176 seqnum = atomic_inc_return(&queue->seqnum) % 0xfff; in a6xx_hfi_send_msg()
194 struct a6xx_hfi_msg_gmu_init_cmd msg = { 0 }; in a6xx_hfi_send_gmu_init()
201 NULL, 0); in a6xx_hfi_send_gmu_init()
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/
Dakebono.dts14 /memreserve/ 0x01f00000 0x00100000; // spin table
21 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
59 cpu-release-addr = <0x0 0x01f00000>;
65 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
71 dcr-reg = <0xffc00000 0x00040000>;
72 #address-cells = <0>;
73 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dakebono.dts14 /memreserve/ 0x01f00000 0x00100000; // spin table
21 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
59 cpu-release-addr = <0x0 0x01f00000>;
65 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
71 dcr-reg = <0xffc00000 0x00040000>;
72 #address-cells = <0>;
73 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/
Da6xx_hfi.c34 return 0; in a6xx_hfi_queue_read()
50 for (i = 0; i < HFI_HEADER_SIZE(hdr); i++) { in a6xx_hfi_queue_read()
78 for (i = 0; i < dwords; i++) { in a6xx_hfi_queue_write()
86 queue->data[index] = 0xfafafafa; in a6xx_hfi_queue_write()
92 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
93 return 0; in a6xx_hfi_queue_write()
161 return 0; in a6xx_hfi_wait_for_ack()
172 seqnum = atomic_inc_return(&queue->seqnum) % 0xfff; in a6xx_hfi_send_msg()
190 struct a6xx_hfi_msg_gmu_init_cmd msg = { 0 }; in a6xx_hfi_send_gmu_init()
197 NULL, 0); in a6xx_hfi_send_gmu_init()
[all …]
/kernel/linux/linux-5.10/drivers/clk/qcom/
Dgcc-sdm660.c41 { P_XO, 0 },
53 { P_XO, 0 },
63 { P_XO, 0 },
77 { P_XO, 0 },
87 { P_XO, 0 },
97 { P_XO, 0 },
115 { P_XO, 0 },
129 { P_XO, 0 },
154 .offset = 0x0,
157 .enable_reg = 0x52000,
[all …]
Dgcc-msm8998.c39 { P_XO, 0 },
53 { P_XO, 0 },
65 { P_XO, 0 },
81 { P_XO, 0 },
93 { P_XO, 0 },
107 { P_XO, 0 },
132 { 250000000, 2000000000, 0 },
137 .offset = 0x0,
142 .enable_reg = 0x52000,
143 .enable_mask = BIT(0),
[all …]
Dgcc-msm8916.c46 { P_XO, 0 },
56 { P_XO, 0 },
68 { P_XO, 0 },
82 { P_XO, 0 },
94 { P_XO, 0 },
104 { P_XO, 0 },
118 { P_XO, 0 },
130 { P_XO, 0, },
140 { P_XO, 0 },
152 { P_XO, 0 },
[all …]
Dgcc-msm8996.c50 { P_XO, 0 },
60 { P_XO, 0 },
70 { P_XO, 0 },
82 { P_XO, 0 },
94 { P_XO, 0 },
106 { P_XO, 0 },
120 { P_XO, 0 },
134 { P_XO, 0 },
152 { P_XO, 0 },
183 .offset = 0x00000,
[all …]
Dgcc-msm8939.c54 .l_reg = 0x21004,
55 .m_reg = 0x21008,
56 .n_reg = 0x2100c,
57 .config_reg = 0x21010,
58 .mode_reg = 0x21000,
59 .status_reg = 0x2101c,
72 .enable_reg = 0x45000,
73 .enable_mask = BIT(0),
85 .l_reg = 0x20004,
86 .m_reg = 0x20008,
[all …]
Dgcc-sc7180.c37 .offset = 0x0,
40 .enable_reg = 0x52010,
41 .enable_mask = BIT(0),
55 { 0x1, 2 },
60 .offset = 0x0,
90 .offset = 0x01000,
93 .enable_reg = 0x52010,
108 .offset = 0x76000,
111 .enable_reg = 0x52010,
126 .offset = 0x13000,
[all …]
Dgcc-sm8250.c37 .offset = 0x0,
40 .enable_reg = 0x52018,
41 .enable_mask = BIT(0),
54 { 0x1, 2 },
59 .offset = 0x0,
76 .offset = 0x76000,
79 .enable_reg = 0x52018,
93 .offset = 0x1c000,
96 .enable_reg = 0x52018,
110 { P_BI_TCXO, 0 },
[all …]
Dgcc-sdm845.c39 { P_BI_TCXO, 0 },
53 { P_BI_TCXO, 0 },
69 { P_BI_TCXO, 0 },
81 { P_BI_TCXO, 0 },
93 { P_BI_TCXO, 0 },
103 { P_BI_TCXO, 0 },
138 { P_BI_TCXO, 0 },
154 .offset = 0x0,
157 .enable_reg = 0x52000,
158 .enable_mask = BIT(0),
[all …]
/kernel/linux/linux-6.6/drivers/clk/qcom/
Dgcc-sdm660.c51 .offset = 0x0,
54 .enable_reg = 0x52000,
55 .enable_mask = BIT(0),
81 .offset = 0x00000,
94 .offset = 0x1000,
97 .enable_reg = 0x52000,
124 .offset = 0x1000,
137 .offset = 0x77000,
140 .enable_reg = 0x52000,
154 .offset = 0x77000,
[all …]
Dgcc-msm8909.c52 { P_XO, 0 },
64 .offset = 0x21000,
67 .enable_reg = 0x45000,
68 .enable_mask = BIT(0),
80 .offset = 0x21000,
94 .l_reg = 0x20004,
95 .m_reg = 0x20008,
96 .n_reg = 0x2000c,
97 .config_reg = 0x20010,
98 .mode_reg = 0x20000,
[all …]
Dgcc-msm8917.c54 .offset = 0x21000,
57 .enable_reg = 0x45008,
72 .offset = 0x21000,
75 .enable_reg = 0x45000,
76 .enable_mask = BIT(0),
89 .offset = 0x21000,
102 { 700000000, 1400000000, 0 },
107 .config_ctl_val = 0x4001055b,
108 .early_output_mask = 0,
114 .offset = 0x22000,
[all …]
Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]
Dgcc-msm8976.c56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a008,
[all …]
Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]
Dgcc-msm8953.c40 .offset = 0x21000,
43 .enable_reg = 0x45000,
44 .enable_mask = BIT(0),
70 .offset = 0x21000,
83 .offset = 0x4a000,
86 .enable_reg = 0x45000,
100 .offset = 0x4a000,
113 { 1000000000, 2000000000, 0 },
118 .config_ctl_val = 0x4001055b,
119 .early_output_mask = 0,
[all …]
Dgcc-sc7180.c36 .offset = 0x0,
39 .enable_reg = 0x52010,
40 .enable_mask = BIT(0),
54 { 0x1, 2 },
59 .offset = 0x0,
89 .offset = 0x01000,
92 .enable_reg = 0x52010,
107 .offset = 0x76000,
110 .enable_reg = 0x52010,
125 .offset = 0x13000,
[all …]
Dgcc-sm8250.c36 .offset = 0x0,
39 .enable_reg = 0x52018,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
75 .offset = 0x76000,
78 .enable_reg = 0x52018,
92 .offset = 0x1c000,
95 .enable_reg = 0x52018,
109 { P_BI_TCXO, 0 },
[all …]
/kernel/linux/linux-6.6/drivers/soc/qcom/
Dllcc-qcom.c21 #define ACTIVATE BIT(0)
23 #define ACT_CLEAR BIT(0)
25 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
27 #define ACT_CTRL_ACT_TRIG BIT(0)
28 #define ACT_CTRL_OPCODE_SHIFT 0x01
29 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
30 #define ATTR1_FIXED_SIZE_SHIFT 0x03
31 #define ATTR1_PRIORITY_SHIFT 0x04
32 #define ATTR1_MAX_CAP_SHIFT 0x10
33 #define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
[all …]

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