| /kernel/linux/linux-5.10/drivers/tty/serial/ |
| D | ip22zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
116 #define X1CLK 0x0 /* x1 clock mode */
117 #define X16CLK 0x40 /* x16 clock mode */
118 #define X32CLK 0x80 /* x32 clock mode */
119 #define X64CLK 0xC0 /* x64 clock mode */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
165 /* Write Register 11 (Clock Mode control) */
[all …]
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| D | zs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
135 #define X1CLK 0x0 /* x1 clock mode */
136 #define X16CLK 0x40 /* x16 clock mode */
137 #define X32CLK 0x80 /* x32 clock mode */
138 #define X64CLK 0xc0 /* x64 clock mode */
144 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
[all …]
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| D | sunzilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
108 #define X1CLK 0x0 /* x1 clock mode */
109 #define X16CLK 0x40 /* x16 clock mode */
110 #define X32CLK 0x80 /* x32 clock mode */
111 #define X64CLK 0xC0 /* x64 clock mode */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
167 /* Write Register 11 (Clock Mode control) */
[all …]
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| D | pmac_zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
74 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
76 return uap->mate; in pmz_get_port_A()
88 writeb(reg, port->control_reg); in read_zsreg()
89 return readb(port->control_reg); in read_zsreg()
95 writeb(reg, port->control_reg); in write_zsreg()
96 writeb(value, port->control_reg); in write_zsreg()
101 return readb(port->data_reg); in read_zsdata()
106 writeb(data, port->data_reg); in write_zsdata()
[all …]
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| /kernel/linux/linux-6.6/drivers/tty/serial/ |
| D | ip22zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
116 #define X1CLK 0x0 /* x1 clock mode */
117 #define X16CLK 0x40 /* x16 clock mode */
118 #define X32CLK 0x80 /* x32 clock mode */
119 #define X64CLK 0xC0 /* x64 clock mode */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
165 /* Write Register 11 (Clock Mode control) */
[all …]
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| D | zs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
135 #define X1CLK 0x0 /* x1 clock mode */
136 #define X16CLK 0x40 /* x16 clock mode */
137 #define X32CLK 0x80 /* x32 clock mode */
138 #define X64CLK 0xc0 /* x64 clock mode */
144 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
[all …]
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| D | sunzilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
108 #define X1CLK 0x0 /* x1 clock mode */
109 #define X16CLK 0x40 /* x16 clock mode */
110 #define X32CLK 0x80 /* x32 clock mode */
111 #define X64CLK 0xC0 /* x64 clock mode */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
167 /* Write Register 11 (Clock Mode control) */
[all …]
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| D | pmac_zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
[all …]
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| /kernel/linux/linux-6.6/drivers/net/hamradio/ |
| D | z8530.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
82 #define X1CLK 0x0 /* x1 clock mode */
83 #define X16CLK 0x40 /* x16 clock mode */
84 #define X32CLK 0x80 /* x32 clock mode */
85 #define X64CLK 0xC0 /* x64 clock mode */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
129 /* Write Register 11 (Clock Mode control) */
131 #define TRxCTC 1 /* TRxC = Transmit clock */
[all …]
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| /kernel/linux/linux-5.10/drivers/net/hamradio/ |
| D | z8530.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
82 #define X1CLK 0x0 /* x1 clock mode */
83 #define X16CLK 0x40 /* x16 clock mode */
84 #define X32CLK 0x80 /* x32 clock mode */
85 #define X64CLK 0xC0 /* x64 clock mode */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
129 /* Write Register 11 (Clock Mode control) */
131 #define TRxCTC 1 /* TRxC = Transmit clock */
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | renesas,5p35023.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 The 5P35023 is a VersaClock programmable clock generator and
14 is designed for low-power, consumer, and high-performance PCI
25 boots. Any configuration not supported by the common clock framework
29 …sas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-pr…
[all …]
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| D | silabs,si514.txt | 1 Binding for Silicon Labs 514 programmable I2C clock generator.
4 This binding uses the common clock binding[1]. Details about the device can be
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible: Shall be "silabs,si514"
13 - reg: I2C device address.
14 - #clock-cells: From common clock bindings: Shall be 0.
17 - clock-output-names: From common clock bindings. Recommended to be "si514".
20 si514: clock-generator@55 {
22 #clock-cells = <0>;
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,v-tc.txt | 2 ------------------------------------
4 The Video Timing Controller is a general purpose video timing generator and
9 - compatible: Must be "xlnx,v-tc-6.1".
11 - reg: Physical base address and length of the registers set for the device.
13 - clocks: Must contain a clock specifier for the VTC core and timing
14 interfaces clock.
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
21 At least one of the xlnx,detector and xlnx,generator properties must be
28 compatible = "xlnx,v-tc-6.1";
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,v-tc.txt | 2 ------------------------------------
4 The Video Timing Controller is a general purpose video timing generator and
9 - compatible: Must be "xlnx,v-tc-6.1".
11 - reg: Physical base address and length of the registers set for the device.
13 - clocks: Must contain a clock specifier for the VTC core and timing
14 interfaces clock.
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
21 At least one of the xlnx,detector and xlnx,generator properties must be
28 compatible = "xlnx,v-tc-6.1";
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
16 Select this option when the clock API in <linux/clk.h> is implemented
22 bool "Common Clock Framework"
28 The common clock framework is a single definition of struct
30 implementation of the clock API in include/linux/clk.h.
37 tristate "Clock driver for WM831x/2x PMICs"
54 tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
62 tristate "Clock driver for Apple SoC NCOs"
[all …]
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| /kernel/linux/linux-6.6/include/soc/fsl/qe/ |
| D | qe.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
33 QE_BRG1, /* Baud Rate Generator 1 */
34 QE_BRG2, /* Baud Rate Generator 2 */
35 QE_BRG3, /* Baud Rate Generator 3 */
36 QE_BRG4, /* Baud Rate Generator 4 */
37 QE_BRG5, /* Baud Rate Generator 5 */
38 QE_BRG6, /* Baud Rate Generator 6 */
39 QE_BRG7, /* Baud Rate Generator 7 */
40 QE_BRG8, /* Baud Rate Generator 8 */
41 QE_BRG9, /* Baud Rate Generator 9 */
[all …]
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| /kernel/linux/linux-5.10/include/soc/fsl/qe/ |
| D | qe.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
39 QE_BRG1, /* Baud Rate Generator 1 */
40 QE_BRG2, /* Baud Rate Generator 2 */
41 QE_BRG3, /* Baud Rate Generator 3 */
42 QE_BRG4, /* Baud Rate Generator 4 */
43 QE_BRG5, /* Baud Rate Generator 5 */
44 QE_BRG6, /* Baud Rate Generator 6 */
45 QE_BRG7, /* Baud Rate Generator 7 */
46 QE_BRG8, /* Baud Rate Generator 8 */
47 QE_BRG9, /* Baud Rate Generator 9 */
[all …]
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| /kernel/linux/linux-6.6/Documentation/gpu/amdgpu/display/ |
| D | dc-glossary.rst | 7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
34 * PCLK: Pixel Clock
35 * SYMCLK: Symbol Clock
36 * SOCCLK: GPU Engine Clock
37 * DISPCLK: Display Clock
38 * DPPCLK: DPP Clock
39 * DCFCLK: Display Controller Fabric Clock
40 * REFCLK: Real Time Reference Clock
42 * FCLK: Fabric Clock
[all …]
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| /kernel/linux/linux-5.10/drivers/iio/frequency/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
5 # Clock Distribution device drivers
6 # Phase-Locked Loop (PLL) frequency synthesizers
12 menu "Clock Generator/Distribution"
15 tristate "Analog Devices AD9523 Low Jitter Clock Generator"
19 Clock Generator. The driver provides direct access via sysfs.
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
|
| /kernel/linux/linux-6.6/Documentation/ABI/testing/ |
| D | sysfs-timecard | 18 uses for clock adjustments.
24 IRIG adjustments from external IRIG-B signal
35 10Mhz signal is used as the 10Mhz reference clock
42 IRIG signal is sent to the IRIG-B module
57 10Mhz output is from the 10Mhz reference clock
58 PHC output PPS is from the PHC clock
59 MAC output PPS is from the Miniature Atomic Clock
62 IRIG output is from the PHC, in IRIG-B format
64 GEN1 output is from frequency generator 1
65 GEN2 output is from frequency generator 2
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ptp/ |
| D | ptp-qoriq.txt | 1 * Freescale QorIQ 1588 timer based PTP clock
5 - compatible Should be "fsl,etsec-ptp" for eTSEC
6 Should be "fsl,fman-ptp-timer" for DPAA FMan
7 Should be "fsl,dpaa2-ptp" for DPAA2
8 Should be "fsl,enetc-ptp" for ENETC
9 - reg Offset and length of the register set for the device
10 - interrupts There should be at least two interrupts. Some devices
13 Clock Properties:
15 - fsl,cksel Timer reference clock source.
16 - fsl,tclk-period Timer reference clock period in nanoseconds.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/ptp/ |
| D | ptp-qoriq.txt | 1 * Freescale QorIQ 1588 timer based PTP clock
5 - compatible Should be "fsl,etsec-ptp" for eTSEC
6 Should be "fsl,fman-ptp-timer" for DPAA FMan
7 Should be "fsl,dpaa2-ptp" for DPAA2
8 Should be "fsl,enetc-ptp" for ENETC
9 - reg Offset and length of the register set for the device
10 - interrupts There should be at least two interrupts. Some devices
13 Clock Properties:
15 - fsl,cksel Timer reference clock source.
16 - fsl,tclk-period Timer reference clock period in nanoseconds.
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wan/ |
| D | z85230.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
103 #define X1CLK 0x0 /* x1 clock mode */
104 #define X16CLK 0x40 /* x16 clock mode */
105 #define X32CLK 0x80 /* x32 clock mode */
106 #define X64CLK 0xC0 /* x64 clock mode */
112 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
121 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
123 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
150 /* Write Register 11 (Clock Mode control) */
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | silabs,si514.txt | 1 Binding for Silicon Labs 514 programmable I2C clock generator.
4 This binding uses the common clock binding[1]. Details about the device can be
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible: Shall be "silabs,si514"
13 - reg: I2C device address.
14 - #clock-cells: From common clock bindings: Shall be 0.
17 - clock-output-names: From common clock bindings. Recommended to be "si514".
20 si514: clock-generator@55 {
22 #clock-cells = <0>;
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| D | armada3700-tbg-clock.txt | 1 * Time Base Generator Clock bindings for Marvell Armada 37xx SoCs
3 Marvell Armada 37xx SoCs provde Time Base Generator clocks which are
6 The TBG clock consumer should specify the desired clock by having the
7 clock ID in its "clocks" phandle cell.
9 The following is a list of provided IDs and clock names on Armada 3700:
16 - compatible : shall be "marvell,armada-3700-tbg-clock"
17 - reg : must be the register address of North Bridge PLL register
18 - #clock-cells : from common clock binding; shall be set to 1
23 compatible = "marvell,armada-3700-tbg-clock";
26 #clock-cells = <1>;
|