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/kernel/linux/linux-5.10/drivers/mtd/maps/
Dphysmap-bt1-rom.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 Physically Mapped Internal ROM driver
22 #include "physmap-bt1-rom.h"
25 * Baikal-T1 SoC ROMs are only accessible by the dword-aligned instructions.
26 * We have to take this into account when implementing the data read-methods.
27 * Note there is no need in bothering with endianness, since both Baikal-T1
33 void __iomem *src = map->virt + ofs; in bt1_rom_map_read()
34 unsigned long shift; in bt1_rom_map_read() local
36 u32 data; in bt1_rom_map_read() local
38 /* Read data within offset dword. */ in bt1_rom_map_read()
[all …]
/kernel/linux/linux-6.6/drivers/mtd/maps/
Dphysmap-bt1-rom.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 Physically Mapped Internal ROM driver
21 #include "physmap-bt1-rom.h"
24 * Baikal-T1 SoC ROMs are only accessible by the dword-aligned instructions.
25 * We have to take this into account when implementing the data read-methods.
26 * Note there is no need in bothering with endianness, since both Baikal-T1
32 void __iomem *src = map->virt + ofs; in bt1_rom_map_read()
33 unsigned int shift; in bt1_rom_map_read() local
35 u32 data; in bt1_rom_map_read() local
37 /* Read data within offset dword. */ in bt1_rom_map_read()
[all …]
/kernel/linux/linux-5.10/drivers/clk/meson/
Daxg.c1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
17 #include "clk-regmap.h"
18 #include "clk-pll.h"
19 #include "clk-mpll.h"
21 #include "meson-eeclk.h"
26 .data = &(struct meson_clk_pll_data){
29 .shift = 30,
34 .shift = 0,
[all …]
Dgxbb.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
13 #include "clk-regmap.h"
14 #include "clk-pll.h"
15 #include "clk-mpll.h"
16 #include "meson-eeclk.h"
17 #include "vid-pll-div.h"
86 .data = &(struct meson_clk_pll_data){
89 .shift = 30,
94 .shift = 0,
[all …]
Dg12a.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
13 #include <linux/clk-provider.h>
19 #include "clk-mpll.h"
20 #include "clk-pll.h"
21 #include "clk-regmap.h"
22 #include "clk-cpu-dyndiv.h"
23 #include "vid-pll-div.h"
24 #include "meson-eeclk.h"
30 .data = &(struct meson_clk_pll_data){
[all …]
Dg12a-aoclk.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-AXG Clock Controller Driver
11 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
15 #include "meson-aoclk.h"
16 #include "g12a-aoclk.h"
18 #include "clk-regmap.h"
19 #include "clk-dualdiv.h"
23 * Register offsets from the data sheet must be multiplied by 4.
45 .data = &(struct clk_regmap_gate_data) { \
[all …]
/kernel/linux/linux-6.6/drivers/clk/meson/
Daxg.c1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
18 #include "clk-regmap.h"
19 #include "clk-pll.h"
20 #include "clk-mpll.h"
22 #include "meson-eeclk.h"
24 #include <dt-bindings/clock/axg-clkc.h>
29 .data = &(struct meson_clk_pll_data){
32 .shift = 30,
[all …]
Da1-peripherals.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
13 #include "a1-peripherals.h"
14 #include "clk-dualdiv.h"
15 #include "clk-regmap.h"
16 #include "meson-clkc-utils.h"
18 #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
21 .data = &(struct clk_regmap_gate_data){
36 .data = &(struct clk_regmap_gate_data){
51 .data = &(struct clk_regmap_gate_data){
[all …]
Dgxbb.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
14 #include "clk-regmap.h"
15 #include "clk-pll.h"
16 #include "clk-mpll.h"
17 #include "meson-eeclk.h"
18 #include "vid-pll-div.h"
20 #include <dt-bindings/clock/gxbb-clkc.h>
89 .data = &(struct meson_clk_pll_data){
92 .shift = 30,
[all …]
Dg12a.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
13 #include <linux/clk-provider.h>
20 #include "clk-mpll.h"
21 #include "clk-pll.h"
22 #include "clk-regmap.h"
23 #include "clk-cpu-dyndiv.h"
24 #include "vid-pll-div.h"
25 #include "meson-eeclk.h"
28 #include <dt-bindings/clock/g12a-clkc.h>
[all …]
Dg12a-aoclk.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-AXG Clock Controller Driver
11 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
16 #include "meson-aoclk.h"
18 #include "clk-regmap.h"
19 #include "clk-dualdiv.h"
21 #include <dt-bindings/clock/g12a-aoclkc.h>
22 #include <dt-bindings/reset/g12a-aoclkc.h>
26 * Register offsets from the data sheet must be multiplied by 4.
[all …]
/kernel/linux/linux-5.10/arch/arm64/lib/
Dcsum.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 Arm Ltd.
5 #include <linux/kasan-checks.h>
10 /* Looks dumb, but generates nice-ish code */
11 static u64 accumulate(u64 sum, u64 data) in accumulate() argument
13 __uint128_t tmp = (__uint128_t)sum + data; in accumulate()
18 * We over-read the buffer and this makes KASAN unhappy. Instead, disable
23 unsigned int offset, shift, sum; in do_csum() local
25 u64 data, sum64 = 0; in do_csum() local
34 * should absolutely not be pointing to anything read-sensitive. We do, in do_csum()
[all …]
/kernel/linux/linux-6.6/arch/arm64/lib/
Dcsum.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 Arm Ltd.
5 #include <linux/kasan-checks.h>
10 /* Looks dumb, but generates nice-ish code */
11 static u64 accumulate(u64 sum, u64 data) in accumulate() argument
13 __uint128_t tmp = (__uint128_t)sum + data; in accumulate()
18 * We over-read the buffer and this makes KASAN unhappy. Instead, disable
23 unsigned int offset, shift, sum; in do_csum() local
25 u64 data, sum64 = 0; in do_csum() local
34 * should absolutely not be pointing to anything read-sensitive. We do, in do_csum()
[all …]
/kernel/linux/linux-5.10/arch/mips/pci/
Dops-vr41xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ops-vr41xx.c, PCI configuration routines for the PCIU of NEC VR4100 series.
5 * Copyright (C) 2001-2003 MontaVista Software Inc.
7 * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
12 * - New creation, NEC VR4122 and VR4131 are supported.
30 return -EINVAL; in set_pci_configuration_address()
39 return -EINVAL; in set_pci_configuration_address()
51 uint32_t data; in pci_config_read() local
54 if (set_pci_configuration_address(bus->number, devfn, where) < 0) in pci_config_read()
57 data = readl(PCICONFDREG); in pci_config_read()
[all …]
/kernel/linux/linux-6.6/arch/sh/drivers/pci/
Dops-sh4.c1 // SPDX-License-Identifier: GPL-2.0
3 * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
5 * Copyright (C) 2002 - 2009 Paul Mundt
11 #include "pci-sh4.h"
17 (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
25 struct pci_channel *chan = bus->sysdata; in sh4_pci_read()
27 u32 data; in sh4_pci_read() local
35 data = pci_read_reg(chan, SH4_PCIPDR); in sh4_pci_read()
40 *val = (data >> ((where & 3) << 3)) & 0xff; in sh4_pci_read()
43 *val = (data >> ((where & 2) << 3)) & 0xffff; in sh4_pci_read()
[all …]
/kernel/linux/linux-5.10/arch/sh/drivers/pci/
Dops-sh4.c1 // SPDX-License-Identifier: GPL-2.0
3 * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
5 * Copyright (C) 2002 - 2009 Paul Mundt
11 #include "pci-sh4.h"
17 (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
25 struct pci_channel *chan = bus->sysdata; in sh4_pci_read()
27 u32 data; in sh4_pci_read() local
35 data = pci_read_reg(chan, SH4_PCIPDR); in sh4_pci_read()
40 *val = (data >> ((where & 3) << 3)) & 0xff; in sh4_pci_read()
43 *val = (data >> ((where & 2) << 3)) & 0xffff; in sh4_pci_read()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dexynos-dw-mshc.txt7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
[all …]
/kernel/linux/linux-5.10/kernel/time/
Dvsyscall.c1 // SPDX-License-Identifier: GPL-2.0
24 vdata[CS_HRES_COARSE].cycle_last = tk->tkr_mono.cycle_last; in update_vdso_data()
25 vdata[CS_HRES_COARSE].mask = tk->tkr_mono.mask; in update_vdso_data()
26 vdata[CS_HRES_COARSE].mult = tk->tkr_mono.mult; in update_vdso_data()
27 vdata[CS_HRES_COARSE].shift = tk->tkr_mono.shift; in update_vdso_data()
28 vdata[CS_RAW].cycle_last = tk->tkr_raw.cycle_last; in update_vdso_data()
29 vdata[CS_RAW].mask = tk->tkr_raw.mask; in update_vdso_data()
30 vdata[CS_RAW].mult = tk->tkr_raw.mult; in update_vdso_data()
31 vdata[CS_RAW].shift = tk->tkr_raw.shift; in update_vdso_data()
35 vdso_ts->sec = tk->xtime_sec + tk->wall_to_monotonic.tv_sec; in update_vdso_data()
[all …]
/kernel/linux/linux-6.6/kernel/time/
Dvsyscall.c1 // SPDX-License-Identifier: GPL-2.0
24 vdata[CS_HRES_COARSE].cycle_last = tk->tkr_mono.cycle_last; in update_vdso_data()
25 vdata[CS_HRES_COARSE].mask = tk->tkr_mono.mask; in update_vdso_data()
26 vdata[CS_HRES_COARSE].mult = tk->tkr_mono.mult; in update_vdso_data()
27 vdata[CS_HRES_COARSE].shift = tk->tkr_mono.shift; in update_vdso_data()
28 vdata[CS_RAW].cycle_last = tk->tkr_raw.cycle_last; in update_vdso_data()
29 vdata[CS_RAW].mask = tk->tkr_raw.mask; in update_vdso_data()
30 vdata[CS_RAW].mult = tk->tkr_raw.mult; in update_vdso_data()
31 vdata[CS_RAW].shift = tk->tkr_raw.shift; in update_vdso_data()
35 vdso_ts->sec = tk->xtime_sec + tk->wall_to_monotonic.tv_sec; in update_vdso_data()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
Dnv50.c29 struct nvkm_device *device = gpio->subdev.device; in nv50_gpio_reset()
30 struct nvkm_bios *bios = device->bios; in nv50_gpio_reset()
33 int ent = -1; in nv50_gpio_reset()
37 u32 data = nvbios_rd32(bios, entry); in nv50_gpio_reset() local
38 u8 line = (data & 0x0000001f); in nv50_gpio_reset()
39 u8 func = (data & 0x0000ff00) >> 8; in nv50_gpio_reset()
40 u8 defs = !!(data & 0x01000000); in nv50_gpio_reset()
41 u8 unk0 = !!(data & 0x02000000); in nv50_gpio_reset()
42 u8 unk1 = !!(data & 0x04000000); in nv50_gpio_reset()
58 nv50_gpio_location(int line, u32 *reg, u32 *shift) in nv50_gpio_location() argument
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
Dnv50.c29 struct nvkm_device *device = gpio->subdev.device; in nv50_gpio_reset()
30 struct nvkm_bios *bios = device->bios; in nv50_gpio_reset()
33 int ent = -1; in nv50_gpio_reset()
37 u32 data = nvbios_rd32(bios, entry); in nv50_gpio_reset() local
38 u8 line = (data & 0x0000001f); in nv50_gpio_reset()
39 u8 func = (data & 0x0000ff00) >> 8; in nv50_gpio_reset()
40 u8 defs = !!(data & 0x01000000); in nv50_gpio_reset()
41 u8 unk0 = !!(data & 0x02000000); in nv50_gpio_reset()
42 u8 unk1 = !!(data & 0x04000000); in nv50_gpio_reset()
58 nv50_gpio_location(int line, u32 *reg, u32 *shift) in nv50_gpio_location() argument
[all …]
/kernel/linux/linux-5.10/sound/soc/sprd/
Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
155 u32 shift = MCDT_DAC_DMA_SHIFT + channel; in sprd_mcdt_dac_dma_enable() local
158 sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(shift), BIT(shift)); in sprd_mcdt_dac_dma_enable()
160 sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(shift)); in sprd_mcdt_dac_dma_enable()
187 writel_relaxed(val, mcdt->base + reg); in sprd_mcdt_dac_write_fifo()
195 *val = readl_relaxed(mcdt->base + reg); in sprd_mcdt_adc_read_fifo()
298 u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan; in sprd_mcdt_dac_dma_ack_select() local
[all …]
/kernel/linux/linux-6.6/sound/soc/sprd/
Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
155 u32 shift = MCDT_DAC_DMA_SHIFT + channel; in sprd_mcdt_dac_dma_enable() local
158 sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(shift), BIT(shift)); in sprd_mcdt_dac_dma_enable()
160 sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(shift)); in sprd_mcdt_dac_dma_enable()
187 writel_relaxed(val, mcdt->base + reg); in sprd_mcdt_dac_write_fifo()
195 *val = readl_relaxed(mcdt->base + reg); in sprd_mcdt_adc_read_fifo()
298 u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan; in sprd_mcdt_dac_dma_ack_select() local
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/samsung/
Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
112 .eint_mask = (1 << (pins)) - 1, \
136 .eint_mask = (1 << (pins)) - 1, \
190 .eint_mask = (1 << (pins)) - 1, \
196 * struct s3c64xx_eint0_data - EINT0 common data
197 * @drvdata: pin controller driver data
208 * struct s3c64xx_eint0_domain_data - EINT0 per-domain data
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/samsung/
Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
112 .eint_mask = (1 << (pins)) - 1, \
136 .eint_mask = (1 << (pins)) - 1, \
190 .eint_mask = (1 << (pins)) - 1, \
196 * struct s3c64xx_eint0_data - EINT0 common data
197 * @drvdata: pin controller driver data
208 * struct s3c64xx_eint0_domain_data - EINT0 per-domain data
[all …]

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