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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dfsl-esdhc.txt1 * Freescale Enhanced Secure Digital Host Controller (eSDHC)
7 by mmc.txt and the properties used by the sdhci-esdhc driver.
10 - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
12 "fsl,mpc8536-esdhc"
13 "fsl,mpc8378-esdhc"
14 "fsl,p2020-esdhc"
15 "fsl,p4080-esdhc"
16 "fsl,t1040-esdhc"
17 "fsl,t4240-esdhc"
19 "fsl,ls1012a-esdhc"
[all …]
Dfsl-imx-esdhc.yaml4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
28 - fsl,imx51-esdhc
29 - fsl,imx53-esdhc
62 due to signal path is too long on the board. Please refer to eSDHC/uSDHC
115 compatible = "fsl,imx51-esdhc";
122 compatible = "fsl,imx51-esdhc";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/
Dfsl-esdhc.txt1 * Freescale Enhanced Secure Digital Host Controller (eSDHC)
7 by mmc.txt and the properties used by the sdhci-esdhc driver.
10 - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
12 "fsl,mpc8536-esdhc"
13 "fsl,mpc8378-esdhc"
14 "fsl,p2020-esdhc"
15 "fsl,p4080-esdhc"
16 "fsl,t1040-esdhc"
17 "fsl,t4240-esdhc"
19 "fsl,ls1012a-esdhc"
[all …]
Dfsl-imx-esdhc.yaml4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
28 - fsl,imx51-esdhc
29 - fsl,imx53-esdhc
39 - const: fsl,imx50-esdhc
40 - const: fsl,imx53-esdhc
111 because the signal path is too long on the board. Please refer to eSDHC/uSDHC
[all …]
/kernel/linux/linux-6.6/drivers/mmc/host/
Dsdhci-of-esdhc.c3 * Freescale eSDHC controller driver.
27 #include "sdhci-esdhc.h"
71 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
72 { .compatible = "fsl,ls1043a-esdhc", .data = &ls1043a_esdhc_clk},
73 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
74 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
75 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
76 { .compatible = "fsl,mpc8379-esdhc" },
77 { .compatible = "fsl,mpc8536-esdhc" },
78 { .compatible = "fsl,esdhc" },
[all …]
Dsdhci-esdhc-mcf.c3 * Freescale eSDHC ColdFire family controller driver, platform bus.
11 #include <linux/platform_data/mmc-esdhc-mcf.h>
14 #include "sdhci-esdhc.h"
21 * Freescale eSDHC has DMA ERR flag at bit 28, not as std spec says, bit 25.
235 * ColdFire eSDHC clock.s in esdhc_mcf_pltfm_set_clock()
238 * +-> / outdiv3 --> eSDHC clock ---> / SDCCLKFS / DVS in esdhc_mcf_pltfm_set_clock()
241 * (8.1.2) eSDHC should be 40 MHz max in esdhc_mcf_pltfm_set_clock()
242 * (25.3.9) eSDHC input is, as example, 96 Mhz ... in esdhc_mcf_pltfm_set_clock()
509 .name = "sdhci-esdhc-mcf",
518 MODULE_DESCRIPTION("SDHCI driver for Freescale ColdFire eSDHC");
Dsdhci-pltfm.c65 if (of_device_is_compatible(np, "fsl,p2020-rev1-esdhc")) in sdhci_get_compatibility()
68 if (of_device_is_compatible(np, "fsl,p2020-esdhc") || in sdhci_get_compatibility()
69 of_device_is_compatible(np, "fsl,p1010-esdhc") || in sdhci_get_compatibility()
70 of_device_is_compatible(np, "fsl,t4240-esdhc") || in sdhci_get_compatibility()
71 of_device_is_compatible(np, "fsl,mpc8536-esdhc")) in sdhci_get_compatibility()
Dsdhci-esdhc.h3 * Freescale eSDHC controller driver generics for OF and pltfm.
16 * Ops and quirks for the Freescale eSDHC controller.
30 * eSDHC register definition
Dsdhci-esdhc-imx.c3 * Freescale eSDHC i.MX controller driver for the platform bus.
30 #include "sdhci-esdhc.h"
127 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
128 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
129 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
130 * Define this macro DMA error INT for fsl eSDHC
150 * The flag tells that the ESDHC controller is an USDHC block that is
218 * struct esdhc_platform_data - platform data for esdhc on i.MX
366 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
367 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci-of-esdhc.c3 * Freescale eSDHC controller driver.
27 #include "sdhci-esdhc.h"
65 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
66 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
67 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
68 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
69 { .compatible = "fsl,mpc8379-esdhc" },
70 { .compatible = "fsl,mpc8536-esdhc" },
71 { .compatible = "fsl,esdhc" },
94 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
[all …]
Dsdhci-esdhc-mcf.c3 * Freescale eSDHC ColdFire family controller driver, platform bus.
11 #include <linux/platform_data/mmc-esdhc-mcf.h>
14 #include "sdhci-esdhc.h"
21 * Freescale eSDHC has DMA ERR flag at bit 28, not as std spec says, bit 25.
235 * ColdFire eSDHC clock.s in esdhc_mcf_pltfm_set_clock()
238 * +-> / outdiv3 --> eSDHC clock ---> / SDCCLKFS / DVS in esdhc_mcf_pltfm_set_clock()
241 * (8.1.2) eSDHC should be 40 MHz max in esdhc_mcf_pltfm_set_clock()
242 * (25.3.9) eSDHC input is, as example, 96 Mhz ... in esdhc_mcf_pltfm_set_clock()
511 .name = "sdhci-esdhc-mcf",
520 MODULE_DESCRIPTION("SDHCI driver for Freescale ColdFire eSDHC");
Dsdhci-pltfm.c66 if (of_device_is_compatible(np, "fsl,p2020-rev1-esdhc")) in sdhci_get_compatibility()
69 if (of_device_is_compatible(np, "fsl,p2020-esdhc") || in sdhci_get_compatibility()
70 of_device_is_compatible(np, "fsl,p1010-esdhc") || in sdhci_get_compatibility()
71 of_device_is_compatible(np, "fsl,t4240-esdhc") || in sdhci_get_compatibility()
72 of_device_is_compatible(np, "fsl,mpc8536-esdhc")) in sdhci_get_compatibility()
Dsdhci-esdhc.h3 * Freescale eSDHC controller driver generics for OF and pltfm.
16 * Ops and quirks for the Freescale eSDHC controller.
30 * eSDHC register definition
Dsdhci-esdhc-imx.c3 * Freescale eSDHC i.MX controller driver for the platform bus.
27 #include <linux/platform_data/mmc-esdhc-imx.h>
31 #include "sdhci-esdhc.h"
122 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
123 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
124 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
125 * Define this macro DMA error INT for fsl eSDHC
145 * The flag tells that the ESDHC controller is an USDHC block that is
300 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
301 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
[all …]
DMakefile87 obj-$(CONFIG_MMC_SDHCI_ESDHC_MCF) += sdhci-esdhc-mcf.o
88 obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
94 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx50.dtsi119 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
131 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
180 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
192 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/
Dimx50.dtsi119 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
131 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
180 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
192 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dqoriq-esdhc-0.dtsi2 * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ]
36 compatible = "fsl,esdhc";
Dpq3-esdhc-0.dtsi2 * PQ3 eSDHC device tree stub [ controller @ offset 0x2e000 ]
36 compatible = "fsl,esdhc";
Dp1020si-post.dtsi154 /include/ "pq3-esdhc-0.dtsi"
156 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
Dc293si-post.dtsi113 /include/ "pq3-esdhc-0.dtsi"
115 compatible = "fsl,c293-esdhc", "fsl,esdhc";
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/fsl/
Dqoriq-esdhc-0.dtsi2 * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ]
36 compatible = "fsl,esdhc";
Dpq3-esdhc-0.dtsi2 * PQ3 eSDHC device tree stub [ controller @ offset 0x2e000 ]
36 compatible = "fsl,esdhc";
Dc293si-post.dtsi113 /include/ "pq3-esdhc-0.dtsi"
115 compatible = "fsl,c293-esdhc", "fsl,esdhc";
Dp1020si-post.dtsi154 /include/ "pq3-esdhc-0.dtsi"
156 compatible = "fsl,p1020-esdhc", "fsl,esdhc";

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