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/kernel/linux/linux-5.10/drivers/dma/dw-edma/
Ddw-edma-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA PCIe driver
13 #include <linux/dma/edma.h>
14 #include <linux/pci-epf.h>
17 #include "dw-edma-core.h"
20 /* eDMA registers location */
24 /* eDMA memory linked list location */
28 /* eDMA memory data location */
39 /* eDMA registers location */
[all …]
Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA core driver
14 #include <linux/err.h>
17 #include <linux/dma/edma.h>
18 #include <linux/dma-mapping.h>
20 #include "dw-edma-core.h"
21 #include "dw-edma-v0-core.h"
23 #include "../virt-dma.h"
28 return &dchan->dev->device; in dchan2dev()
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/kernel/linux/linux-6.6/drivers/dma/
Dmcf-edma-main.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
10 #include <linux/platform_data/dma-mcf-edma.h>
12 #include "fsl-edma-common.h"
20 struct edma_regs *regs = &mcf_edma->regs; in mcf_edma_tx_handler()
24 intmap = ioread32(regs->inth); in mcf_edma_tx_handler()
26 intmap |= ioread32(regs->intl); in mcf_edma_tx_handler()
30 for (ch = 0; ch < mcf_edma->n_chans; ch++) { in mcf_edma_tx_handler()
32 iowrite8(EDMA_MASK_CH(ch), regs->cint); in mcf_edma_tx_handler()
33 fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]); in mcf_edma_tx_handler()
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Dfsl-edma-main.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/dma/fsl-edma.c
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
7 * Driver for the Freescale eDMA engine with flexible channel multiplexing
8 * capability for DMA request sources. The eDMA block can be found on some
12 #include <dt-bindings/dma/fsl-edma.h>
22 #include <linux/dma-mapping.h>
26 #include "fsl-edma-common.h"
32 vchan_synchronize(&fsl_chan->vchan); in fsl_edma_synchronize()
39 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_tx_handler()
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Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
10 #include <linux/dma-mapping.h>
14 #include "fsl-edma-common.h"
48 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
50 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
52 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
56 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
57 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
58 vchan_cookie_complete(&fsl_chan->edesc->vdesc); in fsl_edma_tx_chan_handler()
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/kernel/linux/linux-5.10/drivers/dma/
Dmcf-edma.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
10 #include <linux/platform_data/dma-mcf-edma.h>
12 #include "fsl-edma-common.h"
20 struct edma_regs *regs = &mcf_edma->regs; in mcf_edma_tx_handler()
25 intmap = ioread32(regs->inth); in mcf_edma_tx_handler()
27 intmap |= ioread32(regs->intl); in mcf_edma_tx_handler()
31 for (ch = 0; ch < mcf_edma->n_chans; ch++) { in mcf_edma_tx_handler()
33 iowrite8(EDMA_MASK_CH(ch), regs->cint); in mcf_edma_tx_handler()
35 mcf_chan = &mcf_edma->chans[ch]; in mcf_edma_tx_handler()
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Dfsl-edma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/dma/fsl-edma.c
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
7 * Driver for the Freescale eDMA engine with flexible channel multiplexing
8 * capability for DMA request sources. The eDMA block can be found on some
21 #include "fsl-edma-common.h"
27 vchan_synchronize(&fsl_chan->vchan); in fsl_edma_synchronize()
34 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_tx_handler()
37 intr = edma_readl(fsl_edma, regs->intl); in fsl_edma_tx_handler()
41 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_tx_handler()
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Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
9 #include <linux/dma-mapping.h>
11 #include "fsl-edma-common.h"
47 struct edma_regs *regs = &fsl_chan->edma->regs; in fsl_edma_enable_request()
48 u32 ch = fsl_chan->vchan.chan.chan_id; in fsl_edma_enable_request()
50 if (fsl_chan->edma->drvdata->version == v1) { in fsl_edma_enable_request()
51 edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei); in fsl_edma_enable_request()
52 edma_writeb(fsl_chan->edma, ch, regs->serq); in fsl_edma_enable_request()
57 iowrite8(EDMA_SEEI_SEEI(ch), regs->seei); in fsl_edma_enable_request()
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dfsl-edma.txt1 * Freescale enhanced Direct Memory Access(eDMA) Controller
3 The eDMA channels have multiplex capability by programmble memory-mapped
8 * eDMA Controller
10 - compatible :
11 - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
12 - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp
13 - "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the
15 - reg : Specifies base physical address(s) and size of the eDMA registers.
16 The 1st region is eDMA control register's address and size.
19 - interrupts : A list of interrupt-specifiers, one for each entry in
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/
Dfsl,edma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale enhanced Direct Memory Access(eDMA) Controller
10 The eDMA channels have multiplex capability by programmable
11 memory-mapped registers. channels are split into two groups, called
16 - Peng Fan <peng.fan@nxp.com>
21 - enum:
22 - fsl,vf610-edma
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/kernel/linux/linux-6.6/drivers/dma/dw-edma/
Ddw-edma-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA PCIe driver
13 #include <linux/dma/edma.h>
14 #include <linux/pci-epf.h>
18 #include "dw-edma-core.h"
40 /* eDMA registers location */
42 /* eDMA memory linked list location */
45 /* eDMA memory data location */
56 /* eDMA registers location */
[all …]
Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA core driver
13 #include <linux/err.h>
16 #include <linux/dma/edma.h>
17 #include <linux/dma-mapping.h>
19 #include "dw-edma-core.h"
20 #include "dw-edma-v0-core.h"
21 #include "dw-hdma-v0-core.h"
23 #include "../virt-dma.h"
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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/kernel/linux/linux-5.10/drivers/ata/
Dsata_mv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sata_mv.c - Marvell SATA support
5 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
12 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
18 * --> Develop a low-power-consumption strategy, and implement it.
20 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
22 * --> [Experiment, Marvell value added] Is it possible to use target
23 * mode to cross-connect two Linux boxes with Marvell cards? If so,
31 * 80x1-B2 errata PCI#11:
34 * should be careful to insert those cards only onto PCI-X bus #0,
[all …]
/kernel/linux/linux-6.6/drivers/ata/
Dsata_mv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sata_mv.c - Marvell SATA support
5 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
12 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
18 * --> Develop a low-power-consumption strategy, and implement it.
20 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
22 * --> [Experiment, Marvell value added] Is it possible to use target
23 * mode to cross-connect two Linux boxes with Marvell cards? If so,
31 * 80x1-B2 errata PCI#11:
34 * should be careful to insert those cards only onto PCI-X bus #0,
[all …]
/kernel/linux/linux-6.6/arch/m68k/coldfire/
Ddevice.c2 * device.c -- common ColdFire SoC device support
23 #include <linux/platform_data/edma.h>
24 #include <linux/platform_data/dma-mcf-edma.h>
25 #include <linux/platform_data/mmc-esdhc-mcf.h>
99 #define FEC_NAME "enet-fec"
117 .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
154 .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
195 .end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
346 .end = MCFI2C_BASE0 + MCFI2C_SIZE0 - 1,
357 .name = "imx1-i2c",
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/kernel/linux/linux-5.10/arch/m68k/coldfire/
Ddevice.c2 * device.c -- common ColdFire SoC device support
23 #include <linux/platform_data/edma.h>
24 #include <linux/platform_data/dma-mcf-edma.h>
25 #include <linux/platform_data/mmc-esdhc-mcf.h>
99 #define FEC_NAME "enet-fec"
117 .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
153 .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
195 .end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
346 .end = MCFI2C_BASE0 + MCFI2C_SIZE0 - 1,
357 .name = "imx1-i2c",
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0017_linux_drivers_dma_dmabuf.patch7 Change-Id: Id353bb3186aa6ec13d1725e87d45094eafef8461
9 diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
11 --- a/drivers/dma-buf/dma-buf.c
12 +++ b/drivers/dma-buf/dma-buf.c
13 @@ -377,6 +377,36 @@ static long dma_buf_ioctl(struct file *file,
14 dmabuf = file->private_data;
24 + return -EFAULT;
33 + return -EFAULT;
38 + phys = sg_dma_address(sgt->sgl);
44 + return -EFAULT;
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/kernel/linux/linux-6.6/drivers/dma/ti/
Dedma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI EDMA DMA engine driver
9 #include <linux/dma-mapping.h>
11 #include <linux/err.h>
25 #include <linux/platform_data/edma.h>
28 #include "../virt-dma.h"
42 /* Offsets for EDMA CC global channel registers and their shadows */
66 /* Offsets for EDMA CC global registers */
70 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
100 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
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/kernel/linux/linux-5.10/drivers/dma/ti/
Dedma.c2 * TI EDMA DMA engine driver
17 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
34 #include <linux/platform_data/edma.h>
37 #include "../virt-dma.h"
51 /* Offsets for EDMA CC global channel registers and their shadows */
75 /* Offsets for EDMA CC global registers */
79 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
109 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
110 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dvfxxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #include "vf610-pinfunc.h"
6 #include <dt-bindings/clock/vf610-clock.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/gpio/gpio.h>
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <24000000>;
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
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/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/vf/
Dvfxxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #include "vf610-pinfunc.h"
6 #include <dt-bindings/clock/vf610-clock.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/gpio/gpio.h>
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <24000000>;
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/
Dti,omap-iommu.txt4 - compatible : Should be one of,
5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance
10 - reg : Address space for the configuration registers
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
19 - ti,#tlb-entries : Number of entries in the translation look-aside buffer.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iommu/
Dti,omap-iommu.txt4 - compatible : Should be one of,
5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance
10 - reg : Address space for the configuration registers
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
19 - ti,#tlb-entries : Number of entries in the translation look-aside buffer.
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
22 rtic-a = &rtic_a;
23 rtic-b = &rtic_b;
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