| /kernel/linux/linux-6.6/drivers/tty/serial/ |
| D | milbeaut_usio.c | 67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_stop_tx()
68 port->membase + MLB_USIO_REG_FCR); in mlb_usio_stop_tx()
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE, in mlb_usio_stop_tx()
70 port->membase + MLB_USIO_REG_SCR); in mlb_usio_stop_tx()
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_tx_chars()
79 port->membase + MLB_USIO_REG_FCR); in mlb_usio_tx_chars()
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) & in mlb_usio_tx_chars()
82 port->membase + MLB_USIO_REG_SCR); in mlb_usio_tx_chars()
85 writew(port->x_char, port->membase + MLB_USIO_REG_DR); in mlb_usio_tx_chars()
96 (readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff); in mlb_usio_tx_chars()
[all …]
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| D | qcom_geni_serial.c | 195 uport->membase = devm_platform_ioremap_resource(pdev, 0); in qcom_geni_serial_request_port()
196 if (IS_ERR(uport->membase)) in qcom_geni_serial_request_port()
197 return PTR_ERR(uport->membase); in qcom_geni_serial_request_port()
198 port->se.base = uport->membase; in qcom_geni_serial_request_port()
218 geni_ios = readl(uport->membase + SE_GENI_IOS); in qcom_geni_serial_get_mctrl()
240 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); in qcom_geni_serial_set_mctrl()
262 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; in qcom_geni_serial_main_active()
267 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; in qcom_geni_serial_secondary_active()
290 reg = readl(uport->membase + offset); in qcom_geni_serial_poll_bit()
303 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); in qcom_geni_serial_setup_tx()
[all …]
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| D | timbuart.c | 42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
64 u32 isr = ioread32(port->membase + TIMBUART_ISR); in timbuart_tx_empty()
72 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | in timbuart_flush_buffer()
75 iowrite8(ctl, port->membase + TIMBUART_CTRL); in timbuart_flush_buffer()
76 iowrite32(TXBF, port->membase + TIMBUART_ISR); in timbuart_flush_buffer()
84 while (ioread32(port->membase + TIMBUART_ISR) & RXDP) { in timbuart_rx_chars()
85 u8 ch = ioread8(port->membase + TIMBUART_RXFIFO); in timbuart_rx_chars()
[all …]
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| D | meson_uart.c | 102 val = readl(port->membase + AML_UART_STATUS); in meson_uart_tx_empty()
111 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
113 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
120 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
122 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
134 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
137 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
153 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { in meson_uart_start_tx()
155 writel(port->x_char, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
165 writel(ch, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
[all …]
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| D | amba-pl010.c | 65 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_tx()
67 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_tx()
76 cr = readb(uap->port.membase + UART010_CR); in pl010_start_tx()
78 writel(cr, uap->port.membase + UART010_CR); in pl010_start_tx()
87 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_rx()
89 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_rx()
97 cr = readb(uap->port.membase + UART010_CR); in pl010_disable_ms()
99 writel(cr, uap->port.membase + UART010_CR); in pl010_disable_ms()
108 cr = readb(uap->port.membase + UART010_CR); in pl010_enable_ms()
110 writel(cr, uap->port.membase + UART010_CR); in pl010_enable_ms()
[all …]
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| D | xilinx_uartps.c | 232 while ((readl(port->membase + CDNS_UART_SR) & in cdns_uart_handle_rx()
235 rxbs_status = readl(port->membase + CDNS_UART_RXBS); in cdns_uart_handle_rx()
236 data = readl(port->membase + CDNS_UART_FIFO); in cdns_uart_handle_rx()
320 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); in cdns_uart_handle_tx()
326 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) { in cdns_uart_handle_tx()
328 writel(xmit->buf[xmit->tail], port->membase + CDNS_UART_FIFO); in cdns_uart_handle_tx()
354 isrstatus = readl(port->membase + CDNS_UART_ISR); in cdns_uart_isr()
355 writel(isrstatus, port->membase + CDNS_UART_ISR); in cdns_uart_isr()
369 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS)) in cdns_uart_isr()
458 mreg = readl(port->membase + CDNS_UART_MR); in cdns_uart_set_baud_rate()
[all …]
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| D | fsl_linflexuart.c | 147 ier = readl(port->membase + LINIER); in linflex_stop_tx()
149 writel(ier, port->membase + LINIER); in linflex_stop_tx()
156 ier = readl(port->membase + LINIER); in linflex_stop_rx()
157 writel(ier & ~LINFLEXD_LINIER_DRIE, port->membase + LINIER); in linflex_stop_rx()
164 writeb(c, sport->membase + BDRL); in linflex_put_char()
167 while (((status = readl(sport->membase + UARTSR)) & in linflex_put_char()
172 writel(status | LINFLEXD_UARTSR_DTFTFF, sport->membase + UARTSR); in linflex_put_char()
196 ier = readl(port->membase + LINIER); in linflex_start_tx()
197 writel(ier | LINFLEXD_LINIER_DTIE, port->membase + LINIER); in linflex_start_tx()
235 status = readl(sport->membase + UARTSR); in linflex_rxint()
[all …]
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| D | digicolor-usart.c | 85 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_tx_full()
91 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_rx_empty()
97 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
100 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
105 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
108 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
113 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
116 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
127 writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET); in digicolor_rx_poll()
144 ch = readb_relaxed(port->membase + UA_EMI_REC); in digicolor_uart_rx()
[all …]
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| D | lpc32xx_hs.c | 103 port->membase))) == 0) in wait_for_xmit_empty()
117 port->membase))) < 32) in wait_for_xmit_ready()
128 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); in lpc32xx_hsuart_console_putchar()
168 if (!port->membase) in lpc32xx_hsuart_console_setup()
246 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && in __serial_uart_flush()
248 readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_uart_flush()
257 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
265 LPC32XX_HSUART_IIR(port->membase)); in __serial_lpc32xx_rx()
273 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
281 u32 level = readl(LPC32XX_HSUART_LEVEL(port->membase)); in serial_lpc32xx_tx_ready()
[all …]
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| /kernel/linux/linux-5.10/drivers/tty/serial/ |
| D | milbeaut_usio.c | 67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_stop_tx()
68 port->membase + MLB_USIO_REG_FCR); in mlb_usio_stop_tx()
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE, in mlb_usio_stop_tx()
70 port->membase + MLB_USIO_REG_SCR); in mlb_usio_stop_tx()
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_tx_chars()
79 port->membase + MLB_USIO_REG_FCR); in mlb_usio_tx_chars()
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) & in mlb_usio_tx_chars()
82 port->membase + MLB_USIO_REG_SCR); in mlb_usio_tx_chars()
85 writew(port->x_char, port->membase + MLB_USIO_REG_DR); in mlb_usio_tx_chars()
96 (readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff); in mlb_usio_tx_chars()
[all …]
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| D | qcom_geni_serial.c | 203 uport->membase = devm_platform_ioremap_resource(pdev, 0); in qcom_geni_serial_request_port()
204 if (IS_ERR(uport->membase)) in qcom_geni_serial_request_port()
205 return PTR_ERR(uport->membase); in qcom_geni_serial_request_port()
206 port->se.base = uport->membase; in qcom_geni_serial_request_port()
226 geni_ios = readl(uport->membase + SE_GENI_IOS); in qcom_geni_serial_get_mctrl()
248 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); in qcom_geni_serial_set_mctrl()
297 reg = readl(uport->membase + offset); in qcom_geni_serial_poll_bit()
310 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); in qcom_geni_serial_setup_tx()
312 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); in qcom_geni_serial_setup_tx()
323 writel(M_GENI_CMD_ABORT, uport->membase + in qcom_geni_serial_poll_tx_done()
[all …]
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| D | mvebu-uart.c | 164 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_empty()
186 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
189 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
198 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); in mvebu_uart_start_tx()
203 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
205 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
212 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
214 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
216 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
218 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
[all …]
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| D | timbuart.c | 42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
64 u32 isr = ioread32(port->membase + TIMBUART_ISR); in timbuart_tx_empty()
72 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | in timbuart_flush_buffer()
75 iowrite8(ctl, port->membase + TIMBUART_CTRL); in timbuart_flush_buffer()
76 iowrite32(TXBF, port->membase + TIMBUART_ISR); in timbuart_flush_buffer()
84 while (ioread32(port->membase + TIMBUART_ISR) & RXDP) { in timbuart_rx_chars()
85 u8 ch = ioread8(port->membase + TIMBUART_RXFIFO); in timbuart_rx_chars()
[all …]
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| D | meson_uart.c | 96 val = readl(port->membase + AML_UART_STATUS); in meson_uart_tx_empty()
105 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
107 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
114 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
116 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
128 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
131 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
147 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { in meson_uart_start_tx()
149 writel(port->x_char, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
159 writel(ch, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
[all …]
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| D | fsl_linflexuart.c | 147 ier = readl(port->membase + LINIER); in linflex_stop_tx()
149 writel(ier, port->membase + LINIER); in linflex_stop_tx()
156 ier = readl(port->membase + LINIER); in linflex_stop_rx()
157 writel(ier & ~LINFLEXD_LINIER_DRIE, port->membase + LINIER); in linflex_stop_rx()
168 writeb(c, sport->membase + BDRL); in linflex_transmit_buffer()
171 while (((status = readl(sport->membase + UARTSR)) & in linflex_transmit_buffer()
180 sport->membase + UARTSR); in linflex_transmit_buffer()
195 ier = readl(port->membase + LINIER); in linflex_start_tx()
196 writel(ier | LINFLEXD_LINIER_DTIE, port->membase + LINIER); in linflex_start_tx()
209 writeb(sport->x_char, sport->membase + BDRL); in linflex_txint()
[all …]
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| D | xilinx_uartps.c | 231 while ((readl(port->membase + CDNS_UART_SR) & in cdns_uart_handle_rx()
234 rxbs_status = readl(port->membase + CDNS_UART_RXBS); in cdns_uart_handle_rx()
235 data = readl(port->membase + CDNS_UART_FIFO); in cdns_uart_handle_rx()
319 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); in cdns_uart_handle_tx()
323 !(readl(port->membase + CDNS_UART_SR) & in cdns_uart_handle_tx()
332 port->membase + CDNS_UART_FIFO); in cdns_uart_handle_tx()
370 isrstatus = readl(port->membase + CDNS_UART_ISR); in cdns_uart_isr()
371 writel(isrstatus, port->membase + CDNS_UART_ISR); in cdns_uart_isr()
385 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS)) in cdns_uart_isr()
474 mreg = readl(port->membase + CDNS_UART_MR); in cdns_uart_set_baud_rate()
[all …]
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| D | lpc32xx_hs.c | 103 port->membase))) == 0) in wait_for_xmit_empty()
117 port->membase))) < 32) in wait_for_xmit_ready()
128 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); in lpc32xx_hsuart_console_putchar()
168 if (!port->membase) in lpc32xx_hsuart_console_setup()
247 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && in __serial_uart_flush()
249 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_uart_flush()
258 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
266 LPC32XX_HSUART_IIR(port->membase)); in __serial_lpc32xx_rx()
274 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
288 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_tx()
[all …]
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| D | digicolor-usart.c | 85 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_tx_full()
91 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_rx_empty()
97 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
100 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
105 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
108 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
113 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
116 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
127 writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET); in digicolor_rx_poll()
145 ch = readb_relaxed(port->membase + UA_EMI_REC); in digicolor_uart_rx()
[all …]
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| D | amba-pl010.c | 65 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_tx()
67 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_tx()
76 cr = readb(uap->port.membase + UART010_CR); in pl010_start_tx()
78 writel(cr, uap->port.membase + UART010_CR); in pl010_start_tx()
87 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_rx()
89 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_rx()
97 cr = readb(uap->port.membase + UART010_CR); in pl010_disable_ms()
99 writel(cr, uap->port.membase + UART010_CR); in pl010_disable_ms()
108 cr = readb(uap->port.membase + UART010_CR); in pl010_enable_ms()
110 writel(cr, uap->port.membase + UART010_CR); in pl010_enable_ms()
[all …]
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| /kernel/linux/linux-5.10/drivers/net/mdio/ |
| D | mdio-ipq4019.c | 35 void __iomem *membase; member
43 return readl_poll_timeout(priv->membase + MDIO_CMD_REG, busy, in ipq4019_mdio_wait_busy()
63 data = readl(priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read()
67 writel(data, priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read()
70 writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); in ipq4019_mdio_read()
73 writel(reg, priv->membase + MDIO_DATA_WRITE_REG); in ipq4019_mdio_read()
78 data = readl(priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read()
82 writel(data, priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read()
85 writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); in ipq4019_mdio_read()
91 writel(cmd, priv->membase + MDIO_CMD_REG); in ipq4019_mdio_read()
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/allwinner/ |
| D | sun4i-emac.c | 76 void __iomem *membase; member
98 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
102 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
111 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
115 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
193 writel(0, db->membase + EMAC_CTL_REG); in emac_reset()
195 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); in emac_reset()
246 reg_val = readl(db->membase + EMAC_TX_MODE_REG); in emac_setup()
249 db->membase + EMAC_TX_MODE_REG); in emac_setup()
253 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); in emac_setup()
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/allwinner/ |
| D | sun4i-emac.c | 77 void __iomem *membase; member
108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
121 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
125 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
203 writel(0, db->membase + EMAC_CTL_REG); in emac_reset()
205 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); in emac_reset()
261 reg_val = readl(db->membase + EMAC_RX_CTL_REG); in emac_dma_done_callback()
263 writel(reg_val, db->membase + EMAC_RX_CTL_REG); in emac_dma_done_callback()
266 reg_val = readl(db->membase + EMAC_INT_CTL_REG); in emac_dma_done_callback()
[all …]
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| /kernel/linux/linux-6.6/drivers/net/mdio/ |
| D | mdio-ipq4019.c | 41 void __iomem *membase; member
51 return readl_poll_timeout(priv->membase + MDIO_CMD_REG, busy, in ipq4019_mdio_wait_busy()
66 data = readl(priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read_c45()
70 writel(data, priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read_c45()
73 writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); in ipq4019_mdio_read_c45()
76 writel(reg, priv->membase + MDIO_DATA_WRITE_REG); in ipq4019_mdio_read_c45()
81 writel(cmd, priv->membase + MDIO_CMD_REG); in ipq4019_mdio_read_c45()
89 writel(cmd, priv->membase + MDIO_CMD_REG); in ipq4019_mdio_read_c45()
95 return readl(priv->membase + MDIO_DATA_READ_REG); in ipq4019_mdio_read_c45()
107 data = readl(priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read_c22()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-timberdale.c | 35 void __iomem *membase; member
50 reg = ioread32(tgpio->membase + offset); in timbgpio_update_bit()
57 iowrite32(reg, tgpio->membase + offset); in timbgpio_update_bit()
73 value = ioread32(tgpio->membase + TGPIOVAL); in timbgpio_gpio_get()
110 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_disable()
122 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_enable()
138 ver = ioread32(tgpio->membase + TGPIO_VER); in timbgpio_irq_type()
142 lvr = ioread32(tgpio->membase + TGPIO_LVR); in timbgpio_irq_type()
143 flr = ioread32(tgpio->membase + TGPIO_FLR); in timbgpio_irq_type()
145 bflr = ioread32(tgpio->membase + TGPIO_BFLR); in timbgpio_irq_type()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpio/ |
| D | gpio-timberdale.c | 35 void __iomem *membase; member
50 reg = ioread32(tgpio->membase + offset); in timbgpio_update_bit()
57 iowrite32(reg, tgpio->membase + offset); in timbgpio_update_bit()
73 value = ioread32(tgpio->membase + TGPIOVAL); in timbgpio_gpio_get()
110 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_disable()
122 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_enable()
138 ver = ioread32(tgpio->membase + TGPIO_VER); in timbgpio_irq_type()
142 lvr = ioread32(tgpio->membase + TGPIO_LVR); in timbgpio_irq_type()
143 flr = ioread32(tgpio->membase + TGPIO_FLR); in timbgpio_irq_type()
145 bflr = ioread32(tgpio->membase + TGPIO_BFLR); in timbgpio_irq_type()
[all …]
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