| /kernel/linux/linux-5.10/arch/c6x/platforms/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copied heavily from arm/mach-davinci/clock.c, so:
10 * Copyright (C) 2006-2007 Texas Instruments.
11 * Copyright (C) 2008-2009 Deep Root Systems, LLC
16 #include <linux/clk.h>
27 static void __clk_enable(struct clk *clk) in __clk_enable() argument
29 if (clk->parent) in __clk_enable()
30 __clk_enable(clk->parent); in __clk_enable()
31 clk->usecount++; in __clk_enable()
34 static void __clk_disable(struct clk *clk) in __clk_disable() argument
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| D | plldata.c | 1 // SPDX-License-Identifier: GPL-2.0-only
27 struct clk clkin1 = {
39 .parent = &clkin1,
45 .parent = &c6x_soc_pll1.sysclks[0],
50 .parent = &c6x_soc_pll1.sysclks[0],
55 .parent = &c6x_soc_pll1.sysclks[0],
60 .parent = &c6x_soc_pll1.sysclks[0],
65 .parent = &c6x_soc_pll1.sysclks[0],
70 .parent = &c6x_soc_pll1.sysclks[0],
75 .parent = &c6x_soc_pll1.sysclks[0],
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| /kernel/linux/linux-6.6/drivers/clk/ |
| D | clk_test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Kunit test for clk rate management
5 #include <linux/clk.h>
6 #include <linux/clk-provider.h>
9 #include "clk.h"
28 return ctx->rate; in clk_dummy_recalc_rate()
45 if (req->max_rate < ULONG_MAX) in clk_dummy_maximize_rate()
46 req->rate = req->max_rate; in clk_dummy_maximize_rate()
58 if (req->min_rate > 0) in clk_dummy_minimize_rate()
59 req->rate = req->min_rate; in clk_dummy_minimize_rate()
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| D | clk-gate_test.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Kunit test for clk gate basic type
5 #include <linux/clk.h>
6 #include <linux/clk-provider.h>
16 pdev = platform_device_register_simple("test_gate_device", -1, NULL, 0); in clk_gate_register_test_dev()
19 ret = clk_hw_register_gate(&pdev->dev, "test_gate", NULL, 0, NULL, in clk_gate_register_test_dev()
31 struct clk_hw *parent; in clk_gate_register_test_parent_names() local
34 parent = clk_hw_register_fixed_rate(NULL, "test_parent", NULL, 0, in clk_gate_register_test_parent_names()
36 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent); in clk_gate_register_test_parent_names()
41 KUNIT_EXPECT_PTR_EQ(test, parent, clk_hw_get_parent(ret)); in clk_gate_register_test_parent_names()
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| D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
68 struct clk_core *parent; member
100 #include <trace/events/clk.h>
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| /kernel/linux/linux-5.10/drivers/sh/clk/ |
| D | core.c | 4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
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| D | cpg.c | 5 * Copyright (C) 2010 - 2012 Paul Mundt
11 #include <linux/clk.h>
19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) in sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
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| /kernel/linux/linux-6.6/drivers/sh/clk/ |
| D | core.c | 4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
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| D | cpg.c | 5 * Copyright (C) 2010 - 2012 Paul Mundt
11 #include <linux/clk.h>
19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) in sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
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| /kernel/linux/linux-5.10/arch/arm/mach-ep93xx/ |
| D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-ep93xx/clock.c
12 #include <linux/clk.h>
27 struct clk { struct
28 struct clk *parent; member
35 unsigned long (*get_rate)(struct clk *clk); argument
36 int (*set_rate)(struct clk *clk, unsigned long rate); argument
40 static unsigned long get_uart_rate(struct clk *clk);
42 static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
43 static int set_div_rate(struct clk *clk, unsigned long rate);
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| /kernel/linux/linux-5.10/arch/arm/mach-omap1/ |
| D | clock_data.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/clock_data.c
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
10 * - Clocks that are only available on some chips should be marked with the
16 #include <linux/clk.h>
20 #include <asm/mach-types.h> /* for machine_is_* */
31 /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
42 /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
49 /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
52 /* Some OTG_SYSCON_2-specific bit fields */
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| D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/clock.c
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
17 #include <linux/clk.h>
20 #include <asm/mach-types.h>
31 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
41 unsigned long omap1_uart_recalc(struct clk *clk) in omap1_uart_recalc() argument
43 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
44 return val & 1 << clk->enable_bit ? 48000000 : 12000000; in omap1_uart_recalc()
47 unsigned long omap1_sossi_recalc(struct clk *clk) in omap1_sossi_recalc() argument
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| D | clock.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mach-omap1/clock.h
5 * Copyright (C) 2004 - 2005, 2009 Nokia corporation
13 #include <linux/clk.h>
19 struct clk;
26 #define CLK(dev, con, ck, cp) \ macro
32 .clk = ck, \
36 /* Platform flags for the clkdev-OMAP integration code */
45 #define __clk_get_name(clk) (clk->name) argument
46 #define __clk_get_parent(clk) (clk->parent) argument
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
68 struct clk_core *parent; member
100 #include <trace/events/clk.h>
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| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk-tegra210-emc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clk/tegra.h>
15 #include "clk.h"
37 struct clk *parents[8];
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
70 * CCF assumes that neither the parent nor its rate will change during in tegra210_clk_emc_recalc_rate()
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
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| /kernel/linux/linux-6.6/drivers/clk/tegra/ |
| D | clk-tegra210-emc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clk/tegra.h>
15 #include "clk.h"
37 struct clk *parents[8];
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
70 * CCF assumes that neither the parent nor its rate will change during in tegra210_clk_emc_recalc_rate()
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-scu.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
9 #include <linux/clk-provider.h>
13 #include "clk-scu.h"
21 * struct clk_scu - Description of one SCU clock
33 * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
37 * @clk: clk type of this resource
45 u8 clk; member
50 u8 clk; member
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| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| D | clk-scu.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
18 #include "clk-scu.h"
42 * struct clk_scu - Description of one SCU clock
53 struct clk_hw *parent; member
60 * struct clk_gpr_scu - Description of one SCU GPR clock
76 * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
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| /kernel/linux/linux-5.10/drivers/clk/ti/ |
| D | dpll3xxx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
23 #include <linux/clk.h>
27 #include <linux/clk/ti.h>
40 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
41 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
42 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
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| /kernel/linux/linux-6.6/drivers/clk/ti/ |
| D | dpll3xxx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
23 #include <linux/clk.h>
27 #include <linux/clk/ti.h>
40 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
41 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
42 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
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| /kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh4/ |
| D | clock-sh4-202.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4/clock-sh4-202.c
5 * Additional SH4-202 support for the clock framework
22 static unsigned long emi_clk_recalc(struct clk *clk) in emi_clk_recalc() argument
25 return clk->parent->rate / frqcr3_divisors[idx]; in emi_clk_recalc()
28 static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) in frqcr3_lookup() argument
30 int divisor = clk->parent->rate / rate; in frqcr3_lookup()
45 static struct clk sh4202_emi_clk = {
50 static unsigned long femi_clk_recalc(struct clk *clk) in femi_clk_recalc() argument
53 return clk->parent->rate / frqcr3_divisors[idx]; in femi_clk_recalc()
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| /kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4/ |
| D | clock-sh4-202.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4/clock-sh4-202.c
5 * Additional SH4-202 support for the clock framework
22 static unsigned long emi_clk_recalc(struct clk *clk) in emi_clk_recalc() argument
25 return clk->parent->rate / frqcr3_divisors[idx]; in emi_clk_recalc()
28 static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) in frqcr3_lookup() argument
30 int divisor = clk->parent->rate / rate; in frqcr3_lookup()
45 static struct clk sh4202_emi_clk = {
50 static unsigned long femi_clk_recalc(struct clk *clk) in femi_clk_recalc() argument
53 return clk->parent->rate / frqcr3_divisors[idx]; in femi_clk_recalc()
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| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-sun9i-cpus.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
22 * sun9i_a80_cpus_clk_setup() - Setup function for a80 cpus composite clk
60 reg = readl(cpus->reg); in sun9i_a80_cpus_clk_recalc_rate()
62 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
66 /* clk divider */ in sun9i_a80_cpus_clk_recalc_rate()
73 u8 parent, unsigned long parent_rate) in sun9i_a80_cpus_clk_round() argument
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| /kernel/linux/linux-6.6/drivers/clk/sunxi/ |
| D | clk-sun9i-cpus.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
22 * sun9i_a80_cpus_clk_setup() - Setup function for a80 cpus composite clk
60 reg = readl(cpus->reg); in sun9i_a80_cpus_clk_recalc_rate()
62 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
66 /* clk divider */ in sun9i_a80_cpus_clk_recalc_rate()
73 u8 parent, unsigned long parent_rate) in sun9i_a80_cpus_clk_round() argument
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| /kernel/linux/linux-6.6/drivers/clk/renesas/ |
| D | rcar-gen3-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
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