| /kernel/linux/linux-6.6/drivers/pci/controller/dwc/ |
| D | pcie-armada8k.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
19 #include <linux/pci.h>
20 #include <linux/phy/phy.h>
25 #include "pcie-designware.h"
30 struct dw_pcie *pci; member
33 struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; member
61 * AR/AW Cache defaults: Normal memory, Write-Back, Read / Write
71 #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev)
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| D | pcie-kirin.c | 1 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/phy/phy.h>
23 #include <linux/pci.h>
29 #include "pcie-designware.h"
31 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
56 * Max number of connected PCI slots at an external PCI bridge
60 * in-board Ethernet adapter and the other two connected to M.2 and mini
61 * PCI slots.
75 struct dw_pcie *pci; member
77 struct phy *phy; member
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| D | pci-dra7xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
22 #include <linux/pci.h>
23 #include <linux/phy/phy.h>
32 #include "../../pci.h"
33 #include "pcie-designware.h"
89 struct dw_pcie *pci; member
91 int phy_count; /* DT phy-names count */
92 struct phy **phy; member
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| D | pcie-intel-gw.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/phy/phy.h>
19 #include "../../pci.h"
20 #include "pcie-designware.h"
22 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
64 struct dw_pcie pci; member
70 struct phy *phy; member
86 writel(val, pcie->app_base + ofs); in pcie_app_wr()
92 pcie_update_bits(pcie->app_base, ofs, mask, val); in pcie_app_wr_mask()
97 return dw_pcie_readl_dbi(&pcie->pci, ofs); in pcie_rc_cfg_rd()
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| D | pci-meson.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/pci.h>
18 #include <linux/phy/phy.h>
22 #include "pcie-designware.h"
24 #define to_meson_pcie(x) dev_get_drvdata((x)->dev)
68 struct dw_pcie pci; member
73 struct phy *phy; member
80 struct device *dev = mp->pci.dev; in meson_pcie_get_reset()
93 struct meson_pcie_rc_reset *mrst = &mp->mrst; in meson_pcie_get_resets()
95 mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET); in meson_pcie_get_resets()
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| D | pcie-spear13xx.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2010-2014 ST Microelectronics
17 #include <linux/pci.h>
18 #include <linux/phy/phy.h>
22 #include "pcie-designware.h"
25 struct dw_pcie *pci; member
27 struct phy *phy; member
67 #define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev)
69 static int spear13xx_pcie_start_link(struct dw_pcie *pci) in spear13xx_pcie_start_link() argument
71 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci); in spear13xx_pcie_start_link()
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| D | pcie-histb.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
18 #include <linux/pci.h>
19 #include <linux/phy/phy.h>
24 #include "pcie-designware.h"
26 #define to_histb_pcie(x) dev_get_drvdata((x)->dev)
53 struct dw_pcie *pci; member
58 struct phy *phy; member
69 return readl(histb_pcie->ctrl + reg); in histb_pcie_readl()
74 writel(val, histb_pcie->ctrl + reg); in histb_pcie_writel()
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| D | pci-imx6.c | 1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
23 #include <linux/pci.h>
32 #include <linux/phy/phy.h>
36 #include "pcie-designware.h"
45 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
77 struct dw_pcie *pci; member
99 /* power domain for pcie phy */
101 struct phy *phy; member
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| D | pci-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
17 #include <linux/pci.h>
19 #include <linux/phy/phy.h>
24 #include "pcie-designware.h"
26 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
55 struct dw_pcie pci; member
59 struct phy *phy; member
65 struct device *dev = ep->pci.dev; in exynos_pcie_init_clk_resources()
68 ret = clk_prepare_enable(ep->clk); in exynos_pcie_init_clk_resources()
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| D | pci-keystone.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 * Implementation based on pci-exynos.c and pcie-designware.c
24 #include <linux/phy/phy.h>
30 #include "../../pci.h"
31 #include "pcie-designware.h"
59 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1)))
60 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1)))
84 #define ERR_NONFATAL BIT(2) /* Non-fatal error */
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| D | pcie-dw-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * http://www.rock-chips.com
8 * Author: Simon Xue <xxm@rock-chips.com>
19 #include <linux/phy/phy.h>
24 #include "pcie-designware.h"
34 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
52 struct dw_pcie pci; member
54 struct phy *phy; member
66 return readl_relaxed(rockchip->apb_base + reg); in rockchip_pcie_readl_apb()
72 writel_relaxed(val, rockchip->apb_base + reg); in rockchip_pcie_writel_apb()
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| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | pcie-armada8k.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
19 #include <linux/pci.h>
20 #include <linux/phy/phy.h>
26 #include "pcie-designware.h"
31 struct dw_pcie *pci; member
34 struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; member
62 * AR/AW Cache defaults: Normal memory, Write-Back, Read / Write
72 #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev)
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| D | pci-dra7xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
21 #include <linux/pci.h>
22 #include <linux/phy/phy.h>
31 #include "../../pci.h"
32 #include "pcie-designware.h"
88 struct dw_pcie *pci; member
90 int phy_count; /* DT phy-names count */
91 struct phy **phy; member
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| D | pcie-spear13xx.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2010-2014 ST Microelectronics
17 #include <linux/pci.h>
18 #include <linux/phy/phy.h>
22 #include "pcie-designware.h"
25 struct dw_pcie *pci; member
27 struct phy *phy; member
67 #define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev)
71 struct dw_pcie *pci = spear13xx_pcie->pci; in spear13xx_pcie_establish_link() local
72 struct pcie_port *pp = &pci->pp; in spear13xx_pcie_establish_link()
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| D | pci-meson.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/pci.h>
19 #include <linux/phy/phy.h>
22 #include "pcie-designware.h"
24 #define to_meson_pcie(x) dev_get_drvdata((x)->dev)
68 struct dw_pcie pci; member
73 struct phy *phy; member
80 struct device *dev = mp->pci.dev; in meson_pcie_get_reset()
93 struct meson_pcie_rc_reset *mrst = &mp->mrst; in meson_pcie_get_resets()
95 mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET); in meson_pcie_get_resets()
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| D | pcie-histb.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
18 #include <linux/pci.h>
19 #include <linux/phy/phy.h>
24 #include "pcie-designware.h"
26 #define to_histb_pcie(x) dev_get_drvdata((x)->dev)
53 struct dw_pcie *pci; member
58 struct phy *phy; member
69 return readl(histb_pcie->ctrl + reg); in histb_pcie_readl()
74 writel(val, histb_pcie->ctrl + reg); in histb_pcie_writel()
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| D | pci-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/pci.h>
21 #include <linux/phy/phy.h>
26 #include "pcie-designware.h"
28 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
65 struct dw_pcie *pci; member
71 struct phy *phy; member
85 struct dw_pcie *pci = ep->pci; in exynos5440_pcie_get_mem_resources() local
86 struct device *dev = pci->dev; in exynos5440_pcie_get_mem_resources()
88 ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL); in exynos5440_pcie_get_mem_resources()
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| D | pci-keystone.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 * Implementation based on pci-exynos.c and pcie-designware.c
25 #include <linux/phy/phy.h>
31 #include "../../pci.h"
32 #include "pcie-designware.h"
55 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1)))
56 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1)))
80 #define ERR_NONFATAL BIT(2) /* Non-fatal error */
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| D | pcie-intel-gw.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/phy/phy.h>
17 #include "../../pci.h"
18 #include "pcie-designware.h"
20 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
68 struct dw_pcie pci; member
74 struct phy *phy; member
90 return readl(lpp->app_base + ofs); in pcie_app_rd()
95 writel(val, lpp->app_base + ofs); in pcie_app_wr()
101 pcie_update_bits(lpp->app_base, ofs, mask, val); in pcie_app_wr_mask()
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| /kernel/linux/linux-6.6/drivers/usb/dwc2/ |
| D | pci.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * pci.c - DesignWare HS OTG Controller PCI driver
5 * Copyright (C) 2004-2013 Synopsys, Inc.
9 * Provides the initialization and cleanup entry points for the DWC_otg PCI
19 #include <linux/pci.h>
29 static const char dwc2_driver_name[] = "dwc2-pci";
33 struct platform_device *phy; member
37 * dwc2_pci_remove() - Provides the cleanup entry points for the DWC_otg PCI
40 * @pci: The programming view of DWC_otg PCI
42 static void dwc2_pci_remove(struct pci_dev *pci) in dwc2_pci_remove() argument
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| /kernel/linux/linux-5.10/drivers/usb/dwc2/ |
| D | pci.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * pci.c - DesignWare HS OTG Controller PCI driver
5 * Copyright (C) 2004-2013 Synopsys, Inc.
16 * 3. The names of the above-listed copyright holders may not be used
39 * Provides the initialization and cleanup entry points for the DWC_otg PCI
49 #include <linux/pci.h>
59 static const char dwc2_driver_name[] = "dwc2-pci";
63 struct platform_device *phy; member
68 if (pdev->vendor == PCI_VENDOR_ID_SYNOPSYS && in dwc2_pci_quirks()
69 pdev->device == PCI_PRODUCT_ID_HAPS_HSOTG) { in dwc2_pci_quirks()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | pci-keystone.txt | 3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
22 interrupt-cells: should be set to 1
23 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
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| D | brcm,iproc-pcie.txt | 4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
19 - linux,pci-domain: PCI domain ID. Should be unique for each host controller
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | mpc8641_hpcn_36b.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2008-2009 Freescale Semiconductor Inc.
8 /include/ "mpc8641si-pre.dtsi"
13 #address-cells = <2>;
14 #size-cells = <2>;
29 compatible = "cfi-flash";
31 bank-width = <2>;
32 device-width = <2>;
33 #address-cells = <1>;
34 #size-cells = <1>;
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| D | mpc8641_hpcn.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "mpc8641si-pre.dtsi"
27 compatible = "cfi-flash";
29 bank-width = <2>;
30 device-width = <2>;
31 #address-cells = <1>;
32 #size-cells = <1>;
40 read-only;
49 read-only;
58 tbi-handle = <&tbi0>;
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