| /kernel/linux/linux-6.6/drivers/clk/socfpga/ |
| D | clk-pll-s10.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
9 #include "stratix10-clk.h"
44 unsigned long fdiv, reg, rdiv, qdiv; in n5x_clk_pll_recalc_rate() local
47 /* read VCO1 reg for numerator and denominator */ in n5x_clk_pll_recalc_rate()
48 reg = readl(socfpgaclk->hw.reg + 0x8); in n5x_clk_pll_recalc_rate()
49 fdiv = (reg & SOCFPGA_N5X_PLLDIV_FDIV_MASK) >> SOCFPGA_N5X_PLLDIV_FDIV_SHIFT; in n5x_clk_pll_recalc_rate()
50 rdiv = (reg & SOCFPGA_N5X_PLLDIV_RDIV_MASK); in n5x_clk_pll_recalc_rate()
51 qdiv = (reg & SOCFPGA_N5X_PLLDIV_QDIV_MASK) >> SOCFPGA_N5X_PLLDIV_QDIV_SHIFT; in n5x_clk_pll_recalc_rate()
55 qdiv--; in n5x_clk_pll_recalc_rate()
[all …]
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| D | clk-periph-s10.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
9 #include "stratix10-clk.h"
23 unsigned long shift = socfpgaclk->shift; in n5x_clk_peri_c_clk_recalc_rate()
26 val = readl(socfpgaclk->hw.reg); in n5x_clk_peri_c_clk_recalc_rate()
40 val = readl(socfpgaclk->hw.reg); in clk_peri_c_clk_recalc_rate()
41 val &= GENMASK(SWCTRLBTCLKSEN_SHIFT - 1, 0); in clk_peri_c_clk_recalc_rate()
53 if (socfpgaclk->fixed_div) { in clk_peri_cnt_clk_recalc_rate()
54 div = socfpgaclk->fixed_div; in clk_peri_cnt_clk_recalc_rate()
56 if (socfpgaclk->hw.reg) in clk_peri_cnt_clk_recalc_rate()
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| /kernel/linux/linux-5.10/drivers/clk/socfpga/ |
| D | clk-pll-s10.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
9 #include "stratix10-clk.h"
38 unsigned long arefdiv, reg, mdiv; in agilex_clk_pll_recalc_rate() local
41 /* read VCO1 reg for numerator and denominator */ in agilex_clk_pll_recalc_rate()
42 reg = readl(socfpgaclk->hw.reg); in agilex_clk_pll_recalc_rate()
43 arefdiv = (reg & SOCFPGA_PLL_AREFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT; in agilex_clk_pll_recalc_rate()
48 reg = readl(socfpgaclk->hw.reg + 0x24); in agilex_clk_pll_recalc_rate()
49 mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK; in agilex_clk_pll_recalc_rate()
61 unsigned long reg; in clk_pll_recalc_rate() local
[all …]
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| D | clk-periph-s10.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
9 #include "stratix10-clk.h"
25 val = readl(socfpgaclk->hw.reg); in clk_peri_c_clk_recalc_rate()
26 val &= GENMASK(SWCTRLBTCLKSEN_SHIFT - 1, 0); in clk_peri_c_clk_recalc_rate()
38 if (socfpgaclk->fixed_div) { in clk_peri_cnt_clk_recalc_rate()
39 div = socfpgaclk->fixed_div; in clk_peri_cnt_clk_recalc_rate()
41 if (socfpgaclk->hw.reg) in clk_peri_cnt_clk_recalc_rate()
42 div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); in clk_peri_cnt_clk_recalc_rate()
55 if (socfpgaclk->bypass_reg) { in clk_periclk_get_parent()
[all …]
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| D | clk-pll-a10.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
38 unsigned long divf, divq, reg; in clk_pll_recalc_rate() local
41 /* read VCO1 reg for numerator and denominator */ in clk_pll_recalc_rate()
42 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()
43 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; in clk_pll_recalc_rate()
44 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()
55 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
69 u32 reg; in __socfpga_pll_init() local
72 const char *clk_name = node->name; in __socfpga_pll_init()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | init.c | 31 #include <subdev/bios/init.h>
42 nvkm_printk(init->subdev, lvl, info, "0x%08x[%c]: "fmt, \
43 init->offset, init_exec(init) ? \
44 '0' + (init->nested - 1) : ' ', ##args); \
47 if (init->subdev->debug >= NV_DBG_TRACE) \
55 * init parser control flow helpers
59 init_exec(struct nvbios_init *init) in init_exec() argument
61 return (init->execute == 1) || ((init->execute & 5) == 5); in init_exec()
65 init_exec_set(struct nvbios_init *init, bool exec) in init_exec_set() argument
67 if (exec) init->execute &= 0xfd; in init_exec_set()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | init.c | 31 #include <subdev/bios/init.h>
42 nvkm_printk(init->subdev, lvl, info, "0x%08x[%c]: "fmt, \
43 init->offset, init_exec(init) ? \
44 '0' + (init->nested - 1) : ' ', ##args); \
47 if (init->subdev->debug >= NV_DBG_TRACE) \
55 * init parser control flow helpers
59 init_exec(struct nvbios_init *init) in init_exec() argument
61 return (init->execute == 1) || ((init->execute & 5) == 5); in init_exec()
65 init_exec_set(struct nvbios_init *init, bool exec) in init_exec_set() argument
67 if (exec) init->execute &= 0xfd; in init_exec_set()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/x86/ |
| D | clk-cgu.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
8 #include <linux/clk-provider.h>
12 #include "clk-cgu.h"
14 #define GATE_HW_REG_STAT(reg) ((reg) + 0x0) argument
15 #define GATE_HW_REG_EN(reg) ((reg) + 0x4) argument
16 #define GATE_HW_REG_DIS(reg) ((reg) + 0x8) argument
29 if (list->div_flags & CLOCK_FLAG_VAL_INIT) in lgm_clk_register_fixed()
30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
31 list->div_width, list->div_val); in lgm_clk_register_fixed()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/x86/ |
| D | clk-cgu.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
8 #include <linux/clk-provider.h>
12 #include "clk-cgu.h"
14 #define GATE_HW_REG_STAT(reg) ((reg) + 0x0) argument
15 #define GATE_HW_REG_EN(reg) ((reg) + 0x4) argument
16 #define GATE_HW_REG_DIS(reg) ((reg) + 0x8) argument
29 if (list->div_flags & CLOCK_FLAG_VAL_INIT) in lgm_clk_register_fixed()
30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
31 list->div_width, list->div_val); in lgm_clk_register_fixed()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/berlin/ |
| D | berlin2-avpll.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 #include <linux/clk-provider.h>
15 #include "berlin2-avpll.h"
19 * VCO with 8 channels each, channel 8 is the odd-one-out and does
34 /* BG2/BG2CDs VCO_B has an additional shift of 4 for its VCO_CTRL0 reg */
116 u32 reg; in berlin2_avpll_vco_is_enabled() local
118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
120 reg >>= 4; in berlin2_avpll_vco_is_enabled()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/berlin/ |
| D | berlin2-avpll.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 #include <linux/clk-provider.h>
15 #include "berlin2-avpll.h"
19 * VCO with 8 channels each, channel 8 is the odd-one-out and does
34 /* BG2/BG2CDs VCO_B has an additional shift of 4 for its VCO_CTRL0 reg */
116 u32 reg; in berlin2_avpll_vco_is_enabled() local
118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
120 reg >>= 4; in berlin2_avpll_vco_is_enabled()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| D | clk-busy.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
16 static int clk_busy_wait(void __iomem *reg, u8 shift) in clk_busy_wait() argument
20 while (readl_relaxed(reg) & (1 << shift)) in clk_busy_wait()
22 return -ETIMEDOUT; in clk_busy_wait()
30 void __iomem *reg; member
46 return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate); in clk_busy_divider_recalc_rate()
54 return busy->div_ops->round_rate(&busy->div.hw, rate, prate); in clk_busy_divider_round_rate()
63 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); in clk_busy_divider_set_rate()
65 ret = clk_busy_wait(busy->reg, busy->shift); in clk_busy_divider_set_rate()
[all …]
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| D | clk-lpcg-scu.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
16 #include "clk-scu.h"
25 * struct clk_lpcg_scu - Description of LPCG clock
28 * @reg: register of this LPCG clock
36 void __iomem *reg; member
46 /* e10858 -LPCG clock gating register synchronization errata */
47 static void lpcg_e10858_writel(unsigned long rate, void __iomem *reg, u32 val) in lpcg_e10858_writel() argument
49 writel(val, reg); in lpcg_e10858_writel()
57 * back-to-back writes. in lpcg_e10858_writel()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-busy.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
16 static int clk_busy_wait(void __iomem *reg, u8 shift) in clk_busy_wait() argument
20 while (readl_relaxed(reg) & (1 << shift)) in clk_busy_wait()
22 return -ETIMEDOUT; in clk_busy_wait()
30 void __iomem *reg; member
46 return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate); in clk_busy_divider_recalc_rate()
54 return busy->div_ops->round_rate(&busy->div.hw, rate, prate); in clk_busy_divider_round_rate()
63 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); in clk_busy_divider_set_rate()
65 ret = clk_busy_wait(busy->reg, busy->shift); in clk_busy_divider_set_rate()
[all …]
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| D | clk-lpcg-scu.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
14 #include "clk-scu.h"
23 * struct clk_lpcg_scu - Description of LPCG clock
26 * @reg: register of this LPCG clock
34 void __iomem *reg; member
45 u32 reg, val; in clk_lpcg_scu_enable() local
49 reg = readl_relaxed(clk->reg); in clk_lpcg_scu_enable()
50 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); in clk_lpcg_scu_enable()
53 if (clk->hw_gate) in clk_lpcg_scu_enable()
[all …]
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| D | clk-gate2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
9 #include <linux/clk-provider.h>
22 * prepare - clk_(un)prepare only ensures parent is (un)prepared
23 * enable - clk_enable and clk_disable are functional & control gating
24 * rate - inherits rate from parent. No clk_set_rate support
25 * parent - fixed parent. No clk_set_parent support
30 void __iomem *reg; member
43 u32 reg; in clk_gate2_enable() local
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-gate.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
9 #include <linux/clk-provider.h>
20 * prepare - clk_(un)prepare only ensures parent is (un)prepared
21 * enable - clk_enable and clk_disable are functional & control gating
22 * rate - inherits rate from parent. No clk_set_rate support
23 * parent - fixed parent. No clk_set_parent support
28 if (gate->flags & CLK_GATE_BIG_ENDIAN) in clk_gate_readl()
29 return ioread32be(gate->reg); in clk_gate_readl()
[all …]
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| D | clk-axm5516.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/clk-axm5516.c
16 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/lsi,axm5516-clks.h>
22 * struct axxia_clk - Common struct to all Axxia clocks.
33 * struct axxia_pllclk - Axxia PLL generated clock.
35 * @reg: Offset into regmap for PLL control register
39 u32 reg; member
44 * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the
55 regmap_read(aclk->regmap, pll->reg, &control); in axxia_pllclk_recalc()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/rockchip/ |
| D | clk-inverter.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
15 void __iomem *reg; member
30 val = readl(inv_clock->reg) >> inv_clock->shift; in rockchip_inv_get_phase()
45 return -EINVAL; in rockchip_inv_set_phase()
48 if (inv_clock->flags & ROCKCHIP_INVERTER_HIWORD_MASK) { in rockchip_inv_set_phase()
49 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), in rockchip_inv_set_phase()
50 inv_clock->reg); in rockchip_inv_set_phase()
53 u32 reg; in rockchip_inv_set_phase() local
55 spin_lock_irqsave(inv_clock->lock, flags); in rockchip_inv_set_phase()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| D | clk-inverter.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
15 void __iomem *reg; member
30 val = readl(inv_clock->reg) >> inv_clock->shift; in rockchip_inv_get_phase()
45 return -EINVAL; in rockchip_inv_set_phase()
48 if (inv_clock->flags & ROCKCHIP_INVERTER_HIWORD_MASK) { in rockchip_inv_set_phase()
49 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), in rockchip_inv_set_phase()
50 inv_clock->reg); in rockchip_inv_set_phase()
53 u32 reg; in rockchip_inv_set_phase() local
55 spin_lock_irqsave(inv_clock->lock, flags); in rockchip_inv_set_phase()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/axs10x/ |
| D | pll_clock.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
28 * |-------RESRVED------|-NOUPDATE-|-BYPASS-|-EDGE-|--HIGHTIME--|--LOWTIME--|
33 * reg should be an u32 variable.
36 #define PLL_REG_GET_LOW(reg) \ argument
37 (((reg) & (0x3F << 0)) >> 0)
38 #define PLL_REG_GET_HIGH(reg) \ argument
39 (((reg) & (0x3F << 6)) >> 6)
40 #define PLL_REG_GET_EDGE(reg) \ argument
41 (((reg) & (BIT(12))) ? 1 : 0)
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/axs10x/ |
| D | pll_clock.c | 13 #include <linux/clk-provider.h>
32 * |-------RESRVED------|-NOUPDATE-|-BYPASS-|-EDGE-|--HIGHTIME--|--LOWTIME--|
37 * reg should be an u32 variable.
40 #define PLL_REG_GET_LOW(reg) \ argument
41 (((reg) & (0x3F << 0)) >> 0)
42 #define PLL_REG_GET_HIGH(reg) \ argument
43 (((reg) & (0x3F << 6)) >> 6)
44 #define PLL_REG_GET_EDGE(reg) \ argument
45 (((reg) & (BIT(12))) ? 1 : 0)
46 #define PLL_REG_GET_BYPASS(reg) \ argument
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/ |
| D | clk-gate.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
9 #include <linux/clk-provider.h>
21 * prepare - clk_(un)prepare only ensures parent is (un)prepared
22 * enable - clk_enable and clk_disable are functional & control gating
23 * rate - inherits rate from parent. No clk_set_rate support
24 * parent - fixed parent. No clk_set_parent support
29 if (gate->flags & CLK_GATE_BIG_ENDIAN) in clk_gate_readl()
30 return ioread32be(gate->reg); in clk_gate_readl()
[all …]
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| D | clk-axm5516.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/clk-axm5516.c
16 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/lsi,axm5516-clks.h>
22 * struct axxia_clk - Common struct to all Axxia clocks.
33 * struct axxia_pllclk - Axxia PLL generated clock.
35 * @reg: Offset into regmap for PLL control register
39 u32 reg; member
44 * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the
55 regmap_read(aclk->regmap, pll->reg, &control); in axxia_pllclk_recalc()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/sirf/ |
| D | clk-common.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
20 * - 2 oscillators: osc-26MHz, rtc-32.768KHz
21 * - 3 standard configurable plls: pll1, pll2 & pll3
22 * - 2 exclusive plls: usb phy pll and sata phy pll
23 * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
28 * - dsp domain: gps, mf
29 * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
30 * - sys domain: security
59 static inline unsigned long clkc_readl(unsigned reg) in clkc_readl() argument
[all …]
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