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/kernel/linux/linux-5.10/drivers/hwtracing/intel_th/
Dsth.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Intel Corporation.
16 #include <linux/stm.h>
22 void __iomem *base; member
26 struct stm_data stm; member
33 struct intel_th_channel __iomem *sw_map = sth->channels; in sth_channel()
35 return &sw_map[(master - sth->stm.sw_start) * sth->stm.sw_nchannels + in sth_channel()
70 struct sth_device *sth = container_of(stm_data, struct sth_device, stm); in sth_stm_packet()
73 u64 __iomem *outp = &out->Dn; in sth_stm_packet()
96 writeb_relaxed(*payload, sth->base + reg); in sth_stm_packet()
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/kernel/linux/linux-6.6/drivers/hwtracing/intel_th/
Dsth.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Intel Corporation.
16 #include <linux/stm.h>
22 void __iomem *base; member
26 struct stm_data stm; member
33 struct intel_th_channel __iomem *sw_map = sth->channels; in sth_channel()
35 return &sw_map[(master - sth->stm.sw_start) * sth->stm.sw_nchannels + in sth_channel()
70 struct sth_device *sth = container_of(stm_data, struct sth_device, stm); in sth_stm_packet()
73 u64 __iomem *outp = &out->Dn; in sth_stm_packet()
96 writeb_relaxed(*payload, sth->base + reg); in sth_stm_packet()
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/kernel/linux/linux-5.10/drivers/hwtracing/coresight/
Dcoresight-stm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
8 * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
12 * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
15 * generic STM API by Chunyan Zhang
16 * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
24 #include <linux/coresight-stm.h>
31 #include <linux/stm.h>
33 #include "coresight-priv.h"
85 #define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \
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/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
Dcoresight-stm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
8 * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
12 * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
15 * generic STM API by Chunyan Zhang
16 * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
24 #include <linux/coresight-stm.h>
31 #include <linux/stm.h>
33 #include "coresight-priv.h"
34 #include "coresight-trace-id.h"
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/
Darm,coresight-stm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
23 The STM is a trace source that is integrated into a CoreSight system, designed
24 primarily for high-bandwidth trace of instrumentation embedded into software.
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Dcoresight.txt11 * Required properties for all components *except* non-configurable replicators
12 and non-configurable funnels:
16 - Embedded Trace Buffer (version 1.0):
17 "arm,coresight-etb10", "arm,primecell";
19 - Trace Port Interface Unit:
20 "arm,coresight-tpiu", "arm,primecell";
22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
26 "arm,coresight-tmc", "arm,primecell";
28 - Trace Programmable Funnel:
29 "arm,coresight-dynamic-funnel", "arm,primecell";
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/sprd/
Dsc9836.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #address-cells = <2>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a53";
23 enable-method = "psci";
28 compatible = "arm,cortex-a53";
30 enable-method = "psci";
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
42 compatible = "arm,cortex-a53";
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Dsc9860.dtsi6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/sprd/
Dsc9836.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #address-cells = <2>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a53";
23 enable-method = "psci";
28 compatible = "arm,cortex-a53";
30 enable-method = "psci";
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
42 compatible = "arm,cortex-a53";
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Dsc9860.dtsi6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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/kernel/linux/linux-5.10/Documentation/trace/coresight/
Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
9 ------------
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
43 | |->### | ! | |->### | ! | ! . | || DAP ||
49 *****************************************************************<-|
63 | * ===== F =====<---------|
65 |-->:: CTI ::<!! === N ===
69 |------>&& ETB &&<......II I =======
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/kernel/linux/linux-6.6/Documentation/trace/coresight/
Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
9 ------------
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
43 | |->### | ! | |->### | ! | ! . | || DAP ||
49 *****************************************************************<-|
63 | * ===== F =====<---------|
65 |-->:: CTI ::<!! === N ===
69 |------>&& ETB &&<......II I =======
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/
Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
19 frame-number = <1>;
30 interrupt-names = "mhu_lpri_rx",
32 #mbox-cells = <1>;
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/arm/
Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
19 frame-number = <1>;
31 #mbox-cells = <1>;
33 clock-names = "apb_pclk";
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/kernel/linux/linux-5.10/arch/arm/kernel/
Dentry-header.S1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/asm-offsets.h>
9 #include <asm/uaccess-asm.h>
13 @ -----------------
60 * ARMv7-M exception entry/exit macros.
87 @ we cannot rely on r0-r3 and r12 matching the value saved in the
88 @ exception frame because of tail-chaining. So these have to be
90 ldmia r12!, {r0-r3}
95 sub sp, #PT_REGS_SIZE-S_IP
96 stmdb sp!, {r0-r11}
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/kernel/linux/linux-6.6/arch/x86/include/asm/
Dhyperv-tlfs.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
89 * than inter-processor interrupts
94 * EOI, ICR and TPR rather than their memory-mapped counterparts
97 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
107 * Recommend not using Auto End-Of-Interrupt feature
119 /* Indicates that the hypervisor is nested within a Hyper-V partition. */
155 * flushes gva -> hpa mapping entries. To flush the TLB entries derived
176 /* Hyper-V specific model specific registers (MSRs) */
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/kernel/linux/linux-5.10/drivers/spi/
Dspi-st-ssc4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
56 void __iomem *base; member
75 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
78 count = spi_st->words_remaining; in ssc_write_tx_fifo()
81 if (spi_st->tx_ptr) { in ssc_write_tx_fifo()
82 if (spi_st->bytes_per_word == 1) { in ssc_write_tx_fifo()
83 word = *spi_st->tx_ptr++; in ssc_write_tx_fifo()
85 word = *spi_st->tx_ptr++; in ssc_write_tx_fifo()
86 word = *spi_st->tx_ptr++ | (word << 8); in ssc_write_tx_fifo()
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/kernel/linux/linux-6.6/drivers/spi/
Dspi-st-ssc4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
55 void __iomem *base; member
74 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
77 count = spi_st->words_remaining; in ssc_write_tx_fifo()
80 if (spi_st->tx_ptr) { in ssc_write_tx_fifo()
81 if (spi_st->bytes_per_word == 1) { in ssc_write_tx_fifo()
82 word = *spi_st->tx_ptr++; in ssc_write_tx_fifo()
84 word = *spi_st->tx_ptr++; in ssc_write_tx_fifo()
85 word = *spi_st->tx_ptr++ | (word << 8); in ssc_write_tx_fifo()
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/kernel/linux/linux-6.6/arch/arm/kernel/
Dentry-header.S1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/asm-offsets.h>
9 #include <asm/uaccess-asm.h>
13 @ -----------------
59 * ARMv7-M exception entry/exit macros.
86 @ we cannot rely on r0-r3 and r12 matching the value saved in the
87 @ exception frame because of tail-chaining. So these have to be
89 ldmia r12!, {r0-r3}
94 sub sp, #PT_REGS_SIZE-S_IP
95 stmdb sp!, {r0-r11}
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/kernel/linux/linux-5.10/arch/arm/mm/
Dalignment.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Modifications for ARM processor (c) 1995-2001 Russell King
8 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
33 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
53 #define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
73 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
105 * LDM, STM, LDRD and STRD still need to be handled. in safe_usermode()
108 * CPUs since we spin re-faulting the instruction without in safe_usermode()
159 return -EFAULT; in alignment_proc_write()
161 ai_usermode = safe_usermode(mode - '0', true); in alignment_proc_write()
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/kernel/linux/linux-6.6/arch/arm/mm/
Dalignment.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Modifications for ARM processor (c) 1995-2001 Russell King
8 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
32 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
52 #define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
72 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
104 * LDM, STM, LDRD and STRD still need to be handled. in safe_usermode()
107 * CPUs since we spin re-faulting the instruction without in safe_usermode()
158 return -EFAULT; in alignment_proc_write()
160 ai_usermode = safe_usermode(mode - '0', true); in alignment_proc_write()
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/kernel/linux/linux-5.10/drivers/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 # Rewritten to use lists instead of if-statements.
9 obj-y += irqchip/
10 obj-y += bus/
12 obj-$(CONFIG_GENERIC_PHY) += phy/
15 obj-$(CONFIG_PINCTRL) += pinctrl/
16 obj-$(CONFIG_GPIOLIB) += gpio/
17 obj-y += pwm/
19 obj-y += pci/
21 obj-$(CONFIG_PARISC) += parisc/
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/kernel/linux/linux-6.6/drivers/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 # Rewritten to use lists instead of if-statements.
11 MAKEFLAGS += --include-dir=$(srctree)
14 obj-y += cache/
15 obj-y += irqchip/
16 obj-y += bus/
18 obj-$(CONFIG_GENERIC_PHY) += phy/
21 obj-$(CONFIG_PINCTRL) += pinctrl/
22 obj-$(CONFIG_GPIOLIB) += gpio/
23 obj-y += pwm/
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/kernel/linux/linux-6.6/crypto/
Dansi_cprng.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 * See http://csrc.nist.gov/groups/STM/cavp/documents/rng/931rngext.pdf
91 hexdump("Input DT: ", ctx->DT, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
92 hexdump("Input I: ", ctx->I, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
93 hexdump("Input V: ", ctx->V, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
106 memcpy(tmp, ctx->DT, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
107 output = ctx->I; in _get_more_prng_bytes()
117 xor_vectors(ctx->I, ctx->V, tmp, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
119 output = ctx->rand_data; in _get_more_prng_bytes()
126 if (!memcmp(ctx->rand_data, ctx->last_rand_data, in _get_more_prng_bytes()
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/kernel/linux/linux-5.10/crypto/
Dansi_cprng.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 * See http://csrc.nist.gov/groups/STM/cavp/documents/rng/931rngext.pdf
90 hexdump("Input DT: ", ctx->DT, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
91 hexdump("Input I: ", ctx->I, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
92 hexdump("Input V: ", ctx->V, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
105 memcpy(tmp, ctx->DT, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
106 output = ctx->I; in _get_more_prng_bytes()
116 xor_vectors(ctx->I, ctx->V, tmp, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
118 output = ctx->rand_data; in _get_more_prng_bytes()
125 if (!memcmp(ctx->rand_data, ctx->last_rand_data, in _get_more_prng_bytes()
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