| /kernel/linux/linux-6.6/arch/arm/boot/dts/arm/ |
| D | arm-realview-eb-11mp.dts | 23 /dts-v1/;
24 #include "arm-realview-eb-mp.dtsi"
27 model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C Core Tile";
31 * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.
35 * qemu-system-arm -M realview-eb-mpcore -smp cpus=4
38 #address-cells = <1>;
39 #size-cells = <0>;
40 enable-method = "arm,realview-smp";
46 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
[all …]
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| D | arm-realview-eb-mp.dtsi | 23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "arm-realview-eb.dtsi"
30 * and Cortex-A9 MPCore.
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "arm,realview-eb-soc", "simple-bus";
41 intc: interrupt-controller@1f000100 {
42 compatible = "arm,eb11mp-gic";
43 #interrupt-cells = <3>;
[all …]
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| D | arm-realview-eb.dts | 23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
26 #include "arm-realview-eb.dtsi"
30 compatible = "arm,realview-eb";
34 * This is the core tile with the CPU and GIC etc for the
35 * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache
39 * qemu-system-arm -M realview-eb
40 * Unless specified, QEMU will emulate an ARM926EJ-S core tile.
41 * Switches -cpu arm1136 or -cpu arm1176 emulates the other
[all …]
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| D | arm-realview-eb-a9mp.dts | 23 /dts-v1/;
24 #include "arm-realview-eb-mp.dtsi"
30 * This is the Cortex A9 MPCore tile used with the
34 #address-cells = <1>;
35 #size-cells = <0>;
36 enable-method = "arm,realview-smp";
40 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | arm-realview-eb-11mp.dts | 23 /dts-v1/;
24 #include "arm-realview-eb-mp.dtsi"
27 model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C Core Tile";
31 * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.
35 * qemu-system-arm -M realview-eb-mpcore -smp cpus=4
38 #address-cells = <1>;
39 #size-cells = <0>;
40 enable-method = "arm,realview-smp";
46 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
[all …]
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| D | arm-realview-eb-mp.dtsi | 23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "arm-realview-eb.dtsi"
30 * and Cortex-A9 MPCore.
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "arm,realview-eb-soc", "simple-bus";
41 intc: interrupt-controller@1f000100 {
42 compatible = "arm,eb11mp-gic";
43 #interrupt-cells = <3>;
[all …]
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| D | arm-realview-eb.dts | 23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
26 #include "arm-realview-eb.dtsi"
30 compatible = "arm,realview-eb";
34 * This is the core tile with the CPU and GIC etc for the
35 * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache
39 * qemu-system-arm -M realview-eb
40 * Unless specified, QEMU will emulate an ARM926EJ-S core tile.
41 * Switches -cpu arm1136 or -cpu arm1176 emulates the other
[all …]
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| D | arm-realview-eb-a9mp.dts | 23 /dts-v1/;
24 #include "arm-realview-eb-mp.dtsi"
30 * This is the Cortex A9 MPCore tile used with the
34 #address-cells = <1>;
35 #size-cells = <0>;
36 enable-method = "arm,realview-smp";
40 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/knightslanding/ |
| D | cache.json | 3 …the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might in…
17 "BriefDescription": "Counts the number of L2 cache misses",
24 "BriefDescription": "Counts the total number of L2 cache references.",
31 …cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions …
37 "BriefDescription": "Counts all the load micro-ops retired",
40 "PublicDescription": "This event counts the number of load micro-ops retired.",
45 "BriefDescription": "Counts all the store micro-ops retired",
48 "PublicDescription": "This event counts the number of store micro-ops retired.",
53 …ion": "Counts the loads retired that get the data from the other core in the same tile in M state",
62 "BriefDescription": "Counts the number of load micro-ops retired that miss in L1 D cache",
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/knightslanding/ |
| D | cache.json | 8 …cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictions …
16 …the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might in…
24 "BriefDescription": "Counts the total number of L2 cache references."
32 "BriefDescription": "Counts the number of L2 cache misses"
44 …Description": "This event counts the number of load micro-ops retired that miss in L1 Data cache. …
50 "BriefDescription": "Counts the number of load micro-ops retired that miss in L1 D cache"
59 "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2",
69 "BriefDescription": "Counts the number of load micro-ops retired that miss in the L2",
78 "BriefDescription": "Counts the number of load micro-ops retired that caused micro TLB miss"
87 …ion": "Counts the loads retired that get the data from the other core in the same tile in M state",
[all …]
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| /kernel/linux/linux-6.6/include/uapi/drm/ |
| D | drm_fourcc.h | 39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
222 * IEEE 754-2008 binary16 half-precision float
[all …]
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| D | v3d_drm.h | 2 * Copyright © 2014-2018 Broadcom
63 /* struct drm_v3d_extension - ioctl extensions
65 * Linked-list of generic extensions where the id identify which struct is
76 /* struct drm_v3d_sem - wait/signal semaphore
99 * struct drm_v3d_multi_sync - ioctl extension to add support multiples
124 * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
131 * each CL executes. The VCD cache should be flushed (if necessary)
143 * then writes out the state updates and draw calls necessary per tile
144 * to the tile allocation BO.
148 * clients -- that is left up to the submitter to control
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/ |
| D | nxp,dw100.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
16 architecture. With configurable address mapping look up tables and per tile
24 - nxp,imx8mp-dw100
34 - description: The AXI clock
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/panfrost/ |
| D | panfrost_issues.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. */
16 /* Need way to guarantee that all previously-translated memory accesses
20 /* On job complete with non-done the cache is not flushed */
31 * same time as access to a valid page in the same uTLB cache line ( ==
43 /* Repeatedly Soft-stopping a job chain consisting of (Vertex Shader,
44 * Cache Flush, Tiler) jobs causes DATA_INVALID_FAULT on tiler job. */
53 /* Compute endpoint has a 4-deep queue of tasks, meaning a soft stop
57 /* HT: Tiler returns TERMINATED for non-terminated command */
71 /* Missing cache flush in multi core-group configuration */
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/panfrost/ |
| D | panfrost_issues.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. */
16 /* Need way to guarantee that all previously-translated memory accesses
20 /* On job complete with non-done the cache is not flushed */
31 * same time as access to a valid page in the same uTLB cache line ( ==
43 /* Repeatedly Soft-stopping a job chain consisting of (Vertex Shader,
44 * Cache Flush, Tiler) jobs causes DATA_INVALID_FAULT on tiler job. */
53 /* Compute endpoint has a 4-deep queue of tasks, meaning a soft stop
57 /* HT: Tiler returns TERMINATED for non-terminated command */
71 /* Missing cache flush in multi core-group configuration */
[all …]
|
| /kernel/linux/linux-5.10/include/uapi/drm/ |
| D | v3d_drm.h | 2 * Copyright © 2014-2018 Broadcom
54 * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
61 * each CL executes. The VCD cache should be flushed (if necessary)
73 * then writes out the state updates and draw calls necessary per tile
74 * to the tile allocation BO.
78 * clients -- that is left up to the submitter to control
90 * of tiles (in the case of RCL-only blits).
94 * submitted by other clients -- that is left up to the
109 /* Offset of the tile alloc memory
116 /** Size of the tile alloc memory. */
[all …]
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| D | drm_fourcc.h | 39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
149 * IEEE 754-2008 binary16 half-precision float
167 …010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only …
171 * 16-xx padding occupy lsb
179 * 16-xx padding occupy lsb except Y410
191 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
204 * 1-plane YUV 4:2:0
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| D | intel_fb.c | 1 // SPDX-License-Identifier: MIT
16 #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
21 * the cache-line pairs. The compression state of the cache-line pair
22 * is specified by 2 bits in the CCS. Each CCS cache-line represents
23 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
24 * cache-line-pairs. CCS is always Y tiled."
26 * Since cache line pairs refers to horizontally adjacent cache lines,
27 * each cache line in the CCS corresponds to an area of 32x16 cache
44 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
45 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/ |
| D | nouveau_bo.c | 30 #include <linux/dma-mapping.h>
52 * NV10-NV40 tiling helpers
60 int i = reg - drm->tile.reg; in nv10_bo_update_tile_region()
61 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); in nv10_bo_update_tile_region()
62 struct nvkm_fb_tile *tile = &fb->tile.region[i]; in nv10_bo_update_tile_region() local
64 nouveau_fence_unref(®->fence); in nv10_bo_update_tile_region()
66 if (tile->pitch) in nv10_bo_update_tile_region()
67 nvkm_fb_tile_fini(fb, i, tile); in nv10_bo_update_tile_region()
70 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); in nv10_bo_update_tile_region()
72 nvkm_fb_tile_prog(fb, i, tile); in nv10_bo_update_tile_region()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/ |
| D | nouveau_bo.c | 30 #include <linux/dma-mapping.h>
51 * NV10-NV40 tiling helpers
59 int i = reg - drm->tile.reg; in nv10_bo_update_tile_region()
60 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); in nv10_bo_update_tile_region()
61 struct nvkm_fb_tile *tile = &fb->tile.region[i]; in nv10_bo_update_tile_region() local
63 nouveau_fence_unref(®->fence); in nv10_bo_update_tile_region()
65 if (tile->pitch) in nv10_bo_update_tile_region()
66 nvkm_fb_tile_fini(fb, i, tile); in nv10_bo_update_tile_region()
69 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); in nv10_bo_update_tile_region()
71 nvkm_fb_tile_prog(fb, i, tile); in nv10_bo_update_tile_region()
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/ |
| D | gbefb.c | 4 * Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
5 * Copyright (C) 2002 Vivien Chappelier <vivien.chappelier@linux-mips.org>
14 #include <linux/dma-mapping.h>
44 /* macro for fastest write-though access to the framebuffer */
63 #define TILE_MASK (TILE_SIZE - 1)
87 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
102 .height = -1,
103 .width = -1,
133 .height = -1,
134 .width = -1,
[all …]
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| /kernel/linux/linux-6.6/drivers/video/fbdev/ |
| D | gbefb.c | 4 * Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
5 * Copyright (C) 2002 Vivien Chappelier <vivien.chappelier@linux-mips.org>
14 #include <linux/dma-mapping.h>
44 /* macro for fastest write-though access to the framebuffer */
63 #define TILE_MASK (TILE_SIZE - 1)
87 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
102 .height = -1,
103 .width = -1,
133 .height = -1,
134 .width = -1,
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v7_0.c | 894 * gfx_v7_0_init_microcode - load ucode images from disk
910 switch (adev->asic_type) { in gfx_v7_0_init_microcode()
930 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
933 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
938 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
941 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
946 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
949 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
954 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
957 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v7_0.c | 889 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v7_0_free_microcode()
890 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v7_0_free_microcode()
891 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v7_0_free_microcode()
892 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v7_0_free_microcode()
893 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v7_0_free_microcode()
894 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v7_0_free_microcode()
901 * gfx_v7_0_init_microcode - load ucode images from disk
917 switch (adev->asic_type) { in gfx_v7_0_init_microcode()
938 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v7_0_init_microcode()
943 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); in gfx_v7_0_init_microcode()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/vc4/ |
| D | vc4_drv.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
85 /* The kernel-space BO cache. Tracks buffers that have been
90 /* Array of list heads for entries in the BO cache,
92 * in the cache when allocating.
97 /* List of all BOs in the cache, ordered by age, so we
175 /* The memory used for storing binner tile alloc, tile state,
257 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
261 /* Time in jiffies when the BO was put in vc4->bo_cache. */
264 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
273 * for user-allocated labels.
[all …]
|