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/external/llvm/test/CodeGen/AArch64/
Darm64-neon-mul-div.ll1 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
5 ; CHECK-LABEL: mul8xi8:
6 ; CHECK: mul {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
12 ; CHECK-LABEL: mul16xi8:
13 ; CHECK: mul {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
19 ; CHECK-LABEL: mul4xi16:
20 ; CHECK: mul {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
26 ; CHECK-LABEL: mul8xi16:
27 ; CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
33 ; CHECK-LABEL: mul2xi32:
[all …]
Dfp-dp3.ll1 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -fp-contract=fast | FileCh…
2 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s -check-prefix=C…
8 ; CHECK-LABEL: test_fmadd:
9 ; CHECK-NOFAST-LABEL: test_fmadd:
11 ; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
12 ; CHECK-NOFAST: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
17 ; CHECK-LABEL: test_fmsub:
18 ; CHECK-NOFAST-LABEL: test_fmsub:
19 %nega = fsub float -0.0, %a
21 ; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-neon-mul-div.ll1 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
5 ; CHECK-LABEL: mul8xi8:
6 ; CHECK: mul {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
12 ; CHECK-LABEL: mul16xi8:
13 ; CHECK: mul {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
19 ; CHECK-LABEL: mul4xi16:
20 ; CHECK: mul {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
26 ; CHECK-LABEL: mul8xi16:
27 ; CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
33 ; CHECK-LABEL: mul2xi32:
[all …]
Dfp-dp3.ll1 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -fp-contract=fast | FileCh…
2 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s -check-prefix=C…
8 ; CHECK-LABEL: test_fmadd:
9 ; CHECK-NOFAST-LABEL: test_fmadd:
11 ; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
12 ; CHECK-NOFAST: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
17 ; CHECK-LABEL: test_fmsub:
18 ; CHECK-NOFAST-LABEL: test_fmsub:
19 %nega = fsub float -0.0, %a
21 ; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dglobal_atomics_i64.ll1 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -ch…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck…
3 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -che…
5 ; GCN-LABEL: {{^}}atomic_add_i64_offset:
6 ; CIVI: buffer_atomic_add_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}}
8 ; GFX9: global_atomic_add_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], off offset:32{{$}}
16 ; GCN-LABEL: {{^}}atomic_add_i64_ret_offset:
17 ; CIVI: buffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32…
20 ; GFX9: global_atomic_add_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}…
29 ; GCN-LABEL: {{^}}atomic_add_i64_addr64_offset:
[all …]
Dglobal_atomics.ll1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=G…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck…
3 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -che…
5 ; GCN-LABEL: {{^}}atomic_add_i32_offset:
6 ; SIVI: buffer_atomic_add v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
7 ; GFX9: global_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off offset:16{{$}}
15 ; GCN-LABEL: {{^}}atomic_add_i32_max_neg_offset:
16 ; GFX9: global_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off offset:-4096{{$}}
19 %gep = getelementptr i32, i32 addrspace(1)* %out, i64 -1024
24 ; GCN-LABEL: {{^}}atomic_add_i32_soffset:
[all …]
Dflat_atomics_i64.ll1 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
4 ; GCN-LABEL: {{^}}atomic_add_i64_offset:
5 ; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}}
13 ; GCN-LABEL: {{^}}atomic_add_i64_ret_offset:
14 ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} …
15 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
24 ; GCN-LABEL: {{^}}atomic_add_i64_addr64_offset:
25 ; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}}
34 ; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64_offset:
[all …]
Dflat_atomics.ll1 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,C…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CIV…
3 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GF…
5 ; GCN-LABEL: {{^}}atomic_add_i32_offset:
6 ; CIVI: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
7 ; GFX9: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
15 ; GCN-LABEL: {{^}}atomic_add_i32_max_offset:
16 ; CIVI: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
17 ; GFX9: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:4092{{$}}
25 ; GCN-LABEL: {{^}}atomic_add_i32_max_offset_p1:
[all …]
Dfma-combine.ll1 …-amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contrac…
2 …-amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs -fp-contract…
3 …-amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contrac…
5 ; Note: The SI-FMA conversions of type x * (y + 1) --> x * y + x would be
6 ; beneficial even without fp32 denormals, but they do require no-infs-fp-math
9 declare i32 @llvm.amdgcn.workitem.id.x() #0
10 declare double @llvm.fabs.f64(double) #0
11 declare double @llvm.fma.f64(double, double, double) #0
12 declare float @llvm.fma.f32(float, float, float) #0
14 ; (fadd (fmul x, y), z) -> (fma x, y, z)
[all …]
Dpartial-sgpr-to-vgpr-spills.ll1 ; RUN: llc -O0 -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=ALL …
3 ; FIXME: we should disable sdwa peephole because dead-code elimination, that
9 ; allocated per-frame index, so it's possible to get up with more.
11 ; GCN-LABEL: {{^}}spill_sgprs_to_multiple_vgprs:
25 ; GCN: v_writelane_b32 v0, s4, 0
26 ; GCN-NEXT: v_writelane_b32 v0, s5, 1
27 ; GCN-NEXT: v_writelane_b32 v0, s6, 2
28 ; GCN-NEXT: v_writelane_b32 v0, s7, 3
29 ; GCN-NEXT: v_writelane_b32 v0, s8, 4
30 ; GCN-NEXT: v_writelane_b32 v0, s9, 5
[all …]
Dsdwa-peephole.ll1 …-amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -amdgpu-sdwa-peephole=0 -mattr=-fp64…
2 …-amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -amdgpu-sdwa-peephole -mattr=-fp64-f…
3 …-amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -amdgpu-sdwa-peephole -mattr=-fp64…
5 ; GCN-LABEL: {{^}}add_shr_i32:
6 ; NOSDWA: v_lshrrev_b32_e32 v[[DST:[0-9]+]], 16, v{{[0-9]+}}
7 ; NOSDWA: v_add_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v[[DST]]
8 ; NOSDWA-NOT: v_add_{{(_co)?}}_u32_sdwa
10 ; VI: v_add_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD…
11 ; GFX9: v_add_u32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD sr…
21 ; GCN-LABEL: {{^}}sub_shr_i32:
[all …]
Dmad-combine.ll1 ; Make sure we still form mad even when unsafe math or fp-contract is allowed instead of fma.
3 …-march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=…
4 …-march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contract=fast < %s | FileCheck -enable-var-sc…
5 …-march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -enable-v…
8 …-march=amdgcn -mcpu=tahiti -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | F…
9 …-march=amdgcn -mcpu=verde -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | Fi…
11 declare i32 @llvm.amdgcn.workitem.id.x() #0
12 declare float @llvm.fabs.f32(float) #0
13 declare float @llvm.fma.f32(float, float, float) #0
14 declare float @llvm.fmuladd.f32(float, float, float) #0
[all …]
Dsrl.ll1 …-amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileC…
2 ; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck…
3 …UN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -allow-d…
5 declare i32 @llvm.r600.read.tidig.x() #0
7 ; FUNC-LABEL: {{^}}lshr_i32:
8 ; SI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
9 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
10 ; EG: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
20 ; FUNC-LABEL: {{^}}lshr_v2i32:
21 ; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dvec_cmpd.ll3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s |…
10 ; CHECK-LABEL: v2si64_cmp:
18 ; CHECK-LABEL: v4si64_cmp
19 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
20 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
27 ; CHECK-LABEL: v8si64_cmp
28 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
29 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
30 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dvec_cmpd.ll3 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
4 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
10 ; CHECK-LABEL: v2si64_cmp:
18 ; CHECK-LABEL: v4si64_cmp
19 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
20 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
27 ; CHECK-LABEL: v8si64_cmp
28 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
29 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
30 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dglobal_atomics_i64.ll1 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -ch…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -chec…
4 ; GCN-LABEL: {{^}}atomic_add_i64_offset:
5 ; GCN: buffer_atomic_add_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}}
13 ; GCN-LABEL: {{^}}atomic_add_i64_ret_offset:
14 ; GCN: buffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 …
24 ; GCN-LABEL: {{^}}atomic_add_i64_addr64_offset:
25 ; CI: buffer_atomic_add_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}…
26 ; VI: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}}
35 ; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64_offset:
[all …]
Dflat_atomics_i64.ll1 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
4 ; GCN-LABEL: {{^}}atomic_add_i64_offset:
5 ; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}}
13 ; GCN-LABEL: {{^}}atomic_add_i64_ret_offset:
14 ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} …
15 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
24 ; GCN-LABEL: {{^}}atomic_add_i64_addr64_offset:
25 ; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}}
34 ; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64_offset:
[all …]
Dglobal_atomics.ll1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI …
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -chec…
4 ; FUNC-LABEL: {{^}}atomic_add_i32_offset:
5 ; GCN: buffer_atomic_add v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
13 ; FUNC-LABEL: {{^}}atomic_add_i32_soffset:
14 ; GCN: s_mov_b32 [[SREG:s[0-9]+]], 0x8ca0
15 ; GCN: buffer_atomic_add v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], [[SREG]]{{$}}
23 ; FUNC-LABEL: {{^}}atomic_add_i32_huge_offset:
24 ; SI-DAG: v_mov_b32_e32 v[[PTRLO:[0-9]+]], 0xdeac
25 ; SI-DAG: v_mov_b32_e32 v[[PTRHI:[0-9]+]], 0xabcd
[all …]
Dprivate-element-size.ll1 …-march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-16 -…
2 …-march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-8 -v…
3 …-march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-4 -v…
6 ; ALL-LABEL: {{^}}private_elt_size_v4i32:
8 ; HSA-ELT16: private_element_size = 3
9 ; HSA-ELT8: private_element_size = 2
10 ; HSA-ELT4: private_element_size = 1
13 ; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}}
14 ; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:…
15 ; HSA-ELT16-DAG: buffer_load_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}}
[all …]
Dmad-combine.ll1 ; Make sure we still form mad even when unsafe math or fp-contract is allowed instead of fma.
3 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -chec…
4 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contract=fast < %s | FileCheck -che…
5 …RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck …
8 …-march=amdgcn -mcpu=tahiti -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | F…
9 …-march=amdgcn -mcpu=verde -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | Fi…
11 declare i32 @llvm.amdgcn.workitem.id.x() #0
12 declare float @llvm.fabs.f32(float) #0
13 declare float @llvm.fma.f32(float, float, float) #0
14 declare float @llvm.fmuladd.f32(float, float, float) #0
[all …]
/external/conscrypt/repackaged/common/src/main/java/com/android/org/conscrypt/
DAddressUtils.java9 * http://www.apache.org/licenses/LICENSE-2.0
29 …al String IP_PATTERN = "^(?:(?:(?:25[0-5]|2[0-4][0-9]|[01]?[0-9]?[0-9])\\.){3}(?:25[0-5]|2[0-4][0-…
30 …0-9a-f]{1,4}:){7}(?:[0-9a-f]{1,4}|:))|(?:(?:[0-9a-f]{1,4}:){6}(?::[0-9a-f]{1,4}|(?:(?:25[0-5]|2[0-…
45 return (sniHostname.equalsIgnoreCase("localhost") || sniHostname.indexOf('.') != -1) in isValidSniHostname()
47 && sniHostname.indexOf('\0') == -1; in isValidSniHostname()
54 /* This is here for backwards compatibility for pre-Honeycomb devices. */ in isLiteralIpAddress()
/external/conscrypt/common/src/main/java/org/conscrypt/
DAddressUtils.java8 * http://www.apache.org/licenses/LICENSE-2.0
28 …al String IP_PATTERN = "^(?:(?:(?:25[0-5]|2[0-4][0-9]|[01]?[0-9]?[0-9])\\.){3}(?:25[0-5]|2[0-4][0-…
29 …0-9a-f]{1,4}:){7}(?:[0-9a-f]{1,4}|:))|(?:(?:[0-9a-f]{1,4}:){6}(?::[0-9a-f]{1,4}|(?:(?:25[0-5]|2[0-…
45 || sniHostname.indexOf('.') != -1) in isValidSniHostname()
48 && sniHostname.indexOf('\0') == -1; in isValidSniHostname()
55 /* This is here for backwards compatibility for pre-Honeycomb devices. */ in isLiteralIpAddress()
/external/spirv-llvm/test/SPIRV/
Dlayout.ll1 ; RUN: llvm-as < %s | llvm-spirv -spirv-text -o %t
4 ; CHECK: 119734787 {{[0-9]*}} {{[0-9]*}} {{[0-9]*}} 0
5 ; CHECK-NEXT: {{[0-9]*}} Capability
6 ; CHECK: {{[0-9]*}} ExtInstImport
7 ; CHECK-NEXT: {{[0-9]*}} MemoryModel
8 ; CHECK-NEXT: {{[0-9]*}} EntryPoint
9 ; CHECK-NEXT: {{[0-9]*}} Source
11 ; CHECK-NOT: {{[0-9]*}} Capability
12 ; CHECK-NOT: {{[0-9]*}} ExtInstImport
13 ; CHECK-NOT: {{[0-9]*}} MemoryModel
[all …]
/external/icu/icu4c/source/test/testdata/
Dregextst.txt3 # Copyright (c) 2001-2015 International Business Machines
17 # if any, is group 0, as in <0>matched text</0>
24 # s dot-matches-all mode
25 # m multi-line mode.
26 # ($ and ^ match at embedded new-lines)
27 # D Unix Lines mode (only recognize 0x0a as new-line)
34 # 2-9 a digit between 2 and 9, specifies the number of
42 # a Use non-Anchoring Bounds.
53 # Look-ahead expressions
55 "(?!0{5})(\d{5})" "<0><1>00001</1></0>zzzz"
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/external/python/dateutil/dateutil/test/
Dtest_rrule.py1 # -*- coding: utf-8 -*-
35 dtstart=datetime(1997, 9, 2, 9, 0))),
47 dtstart=datetime(1997, 9, 2, 9, 0))),
48 [datetime(1997, 9, 2, 9, 0),
49 datetime(1998, 9, 2, 9, 0),
50 datetime(1999, 9, 2, 9, 0)])
56 dtstart=datetime(1997, 9, 2, 9, 0))),
57 [datetime(1997, 9, 2, 9, 0),
58 datetime(1999, 9, 2, 9, 0),
59 datetime(2001, 9, 2, 9, 0)])
[all …]

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