| /art/runtime/ |
| D | reference_table_test.cc | 84 ReferenceTable rt("test", 0, 11); in TEST_F() local
89 rt.Dump(oss); in TEST_F()
91 EXPECT_EQ(0U, rt.Size()); in TEST_F()
95 rt.Remove(nullptr); in TEST_F()
96 EXPECT_EQ(0U, rt.Size()); in TEST_F()
99 rt.Remove(o1.Get()); in TEST_F()
100 EXPECT_EQ(0U, rt.Size()); in TEST_F()
104 rt.Add(o1.Get()); in TEST_F()
105 EXPECT_EQ(1U, rt.Size()); in TEST_F()
107 rt.Dump(oss); in TEST_F()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 99 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR() argument
102 CHECK_NE(rt, kNoGpuRegister); in EmitR()
106 static_cast<uint32_t>(rt) << kRtShift | in EmitR()
126 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, in EmitRtd() argument
128 CHECK_NE(rt, kNoGpuRegister); in EmitRtd()
132 static_cast<uint32_t>(rt) << kRtShift | in EmitRtd()
139 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { in EmitI() argument
141 CHECK_NE(rt, kNoGpuRegister); in EmitI()
144 static_cast<uint32_t>(rt) << kRtShift | in EmitI()
303 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Addu() argument
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| D | assembler_mips64.h | 446 void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
447 void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
448 void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
449 void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
450 void Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
451 void Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
453 void MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
454 void MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
455 void DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
456 void ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
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| D | assembler_mips64_test.cc | 2601 void Dinsu(mips64::GpuRegister rt, mips64::GpuRegister rs, int pos, int size) { in Dinsu()
2608 regs_[rt] = (regs_[rt] & dsk_mask) | ((regs_[rs] & src_mask) << pos); in Dinsu()
2610 void Dsll(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { in Dsll()
2611 regs_[rd] = regs_[rt] << (shamt & 0x1f); in Dsll()
2613 void Dsll32(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { in Dsll32()
2614 regs_[rd] = regs_[rt] << (32 + (shamt & 0x1f)); in Dsll32()
2616 void Dsrl(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { in Dsrl()
2617 regs_[rd] = regs_[rt] >> (shamt & 0x1f); in Dsrl()
2619 void Dsrl32(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { in Dsrl32()
2620 regs_[rd] = regs_[rt] >> (32 + (shamt & 0x1f)); in Dsrl32()
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 257 Register rt, in EmitR() argument
262 CHECK_NE(rt, kNoRegister); in EmitR()
266 static_cast<uint32_t>(rt) << kRtShift | in EmitR()
274 uint32_t MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { in EmitI() argument
276 CHECK_NE(rt, kNoRegister); in EmitI()
279 static_cast<uint32_t>(rt) << kRtShift | in EmitI()
454 void MipsAssembler::Addu(Register rd, Register rs, Register rt) { in Addu() argument
455 DsFsmInstr(EmitR(0, rs, rt, rd, 0, 0x21)).GprOuts(rd).GprIns(rs, rt); in Addu()
458 void MipsAssembler::Addiu(Register rt, Register rs, uint16_t imm16, MipsLabel* patcher_label) { in Addiu() argument
462 DsFsmInstr(EmitI(0x9, rs, rt, imm16), patcher_label).GprOuts(rt).GprIns(rs); in Addiu()
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| D | assembler_mips.h | 299 void Addu(Register rd, Register rs, Register rt);
300 void Addiu(Register rt, Register rs, uint16_t imm16, MipsLabel* patcher_label);
301 void Addiu(Register rt, Register rs, uint16_t imm16);
302 void Subu(Register rd, Register rs, Register rt);
304 void MultR2(Register rs, Register rt); // R2
305 void MultuR2(Register rs, Register rt); // R2
306 void DivR2(Register rs, Register rt); // R2
307 void DivuR2(Register rs, Register rt); // R2
308 void MulR2(Register rd, Register rs, Register rt); // R2
309 void DivR2(Register rd, Register rs, Register rt); // R2
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| /art/test/800-smali/ |
| D | jni.cc | 31 Runtime* rt = Runtime::Current(); in Java_Main_isAotVerified() local
36 bool ret = rt->GetClassLinker()->VerifyClassUsingOatFile(dex_file, klass, oat_file_class_status); in Java_Main_isAotVerified()
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| /art/runtime/interpreter/mterp/mips/ |
| D | main.S | 161 #define SEB(rd, rt) \ argument
162 seb rd, rt
163 #define SEH(rd, rt) \ argument
164 seh rd, rt
168 #define SEB(rd, rt) \ argument
169 sll rd, rt, 24; \
171 #define SEH(rd, rt) \ argument
172 sll rd, rt, 16; \
189 #define JR(rt) \ argument
190 jic rt, 0
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| /art/test/961-default-iface-resolution-gen/ |
| D | run | 18 ./default-run "$@" --dex2oat-timeout 120 --dex2oat-rt-timeout 180
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| /art/disassembler/ |
| D | disassembler_mips.cc | 523 uint32_t rt = (instruction >> 16) & 0x1f; // I-type, R-type. in Dump() local
565 args << "cc" << (rt >> 2); in Dump()
656 case 'T': args << RegName(rt); break; in Dump()
657 case 't': args << 'f' << rt; break; in Dump()
662 case 'n': args << 'w' << rt; break; in Dump()
820 if (((op == 0x36 || op == 0x3E) && rs == 0 && rt != 0) && // ji[al]c in Dump()
823 ((last_instr_ >> 21) & 0x1F) == rt) { in Dump()
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| /art/compiler/optimizing/ |
| D | loop_optimization.cc | 1129 HInstruction* rt = Insert( in Vectorize() local
1134 HSelect(rt, vtc, graph_->GetConstant(induc_type, 0), kNoDexPc)); in Vectorize()
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| D | code_generator_arm_vixl.cc | 106 static inline bool CanEmitNarrowLdr(vixl32::Register rt, vixl32::Register rn, uint32_t offset) { in CanEmitNarrowLdr() argument
107 return rt.IsLow() && rn.IsLow() && offset < 32u; in CanEmitNarrowLdr()
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