Searched refs:BEXTR (Results 1 – 22 of 22) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 1145 X86_INTRINSIC_DATA(bmi_bextr_32, INTR_TYPE_2OP, X86ISD::BEXTR, 0),
1146 X86_INTRINSIC_DATA(bmi_bextr_64, INTR_TYPE_2OP, X86ISD::BEXTR, 0),
1244 X86_INTRINSIC_DATA(tbm_bextri_u32, INTR_TYPE_2OP, X86ISD::BEXTR, 0),
1245 X86_INTRINSIC_DATA(tbm_bextri_u64, INTR_TYPE_2OP, X86ISD::BEXTR, 0),
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| D | X86ScheduleSLM.td | 137 // BMI1 BEXTR, BMI2 BZHI
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| D | X86ISelLowering.h | 356 BEXTR, enumerator
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| D | X86ScheduleBtVer2.td | 203 // BMI1 BEXTR, BMI2 BZHI
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| D | X86Schedule.td | 155 // BMI1 BEXTR, BMI2 BZHI
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| D | X86ScheduleAtom.td | 144 // BMI1 BEXTR, BMI2 BZHI
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| D | X86SchedSandyBridge.td | 162 // BMI1 BEXTR, BMI2 BZHI
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| D | X86ScheduleZnver1.td | 213 // BMI1 BEXTR, BMI2 BZHI
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| D | X86SchedSkylakeClient.td | 157 // BMI1 BEXTR, BMI2 BZHI
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| D | X86SchedBroadwell.td | 158 // BMI1 BEXTR, BMI2 BZHI
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| D | X86SchedHaswell.td | 167 // BMI1 BEXTR, BMI2 BZHI
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| D | X86ISelDAGToDAG.cpp | 2606 SDValue New = CurDAG->getNode(X86ISD::BEXTR, dl, NVT, in matchBEXTRFromAnd()
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| D | X86SchedSkylakeServer.td | 157 // BMI1 BEXTR, BMI2 BZHI
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| D | X86InstrInfo.td | 292 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
2476 // Use BEXTR for 64-bit 'and' with large immediate 'mask'.
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| D | X86InstrCompiler.td | 2086 // custom combines and+srl into BEXTR. We use these patterns to avoid a bunch
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| D | X86ISelLowering.cpp | 26041 case X86ISD::BEXTR: return "X86ISD::BEXTR"; in getTargetNodeName()
37125 return DAG.getNode(X86ISD::BEXTR, SDLoc(N), VT, Op0, in combineBEXTR()
39655 case X86ISD::BEXTR: return combineBEXTR(N, DAG, DCI, Subtarget); in PerformDAGCombine()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 346 BEXTR, enumerator
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| D | X86SchedHaswell.td | 894 // BEXTR.
896 def : InstRW<[Write2P0156_Lat2], (instregex "BEXTR(32|64)rr")>;
898 def : InstRW<[Write2P0156_Lat2Ld], (instregex "BEXTR(32|64)rm")>;
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| D | X86InstrInfo.td | 273 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
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| D | X86ISelLowering.cpp | 22217 case X86ISD::BEXTR: return "X86ISD::BEXTR"; in getTargetNodeName()
28280 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0), in combineAnd()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenFastISel.inc | 8574 // FastEmit functions for X86ISD::BEXTR.
11990 case X86ISD::BEXTR: return fastEmit_X86ISD_BEXTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
12636 // FastEmit functions for X86ISD::BEXTR.
14427 case X86ISD::BEXTR: return fastEmit_X86ISD_BEXTR_ri(VT, RetVT, Op0, Op0IsKill, imm1);
14912 // FastEmit functions for X86ISD::BEXTR.
14940 …case X86ISD::BEXTR: return fastEmit_X86ISD_BEXTR_ri_Predicate_i64immSExt32(VT, RetVT, Op0, Op0IsKi…
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| /external/syzkaller/pkg/ifuzz/gen/ |
| D | all-enc-instructions.txt | 25232 ICLASS : BEXTR
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