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Searched refs:BMI2 (Results 1 – 25 of 38) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dclear-lowbits.ll5 …-mattr=+bmi,+tbm,+bmi2 < %s | FileCheck %s --check-prefixes=CHECK,X86,BMI2,X86-BMI2,FALLBACK3,X86-…
6 …-mattr=+bmi,-tbm,+bmi2 < %s | FileCheck %s --check-prefixes=CHECK,X86,BMI2,X86-BMI2,FALLBACK4,X86-…
10 …-mattr=+bmi,+tbm,+bmi2 < %s | FileCheck %s --check-prefixes=CHECK,X64,BMI2,X64-BMI2,FALLBACK3,X64-…
11 …-mattr=+bmi,-tbm,+bmi2 < %s | FileCheck %s --check-prefixes=CHECK,X64,BMI2,X64-BMI2,FALLBACK4,X64-…
18 ; are equivalent, but we prefer the second variant if we have BMI2.
106 ; X86-BMI2-LABEL: clear_lowbits16_c0:
107 ; X86-BMI2: # %bb.0:
108 ; X86-BMI2-NEXT: movzwl {{[0-9]+}}(%esp), %eax
109 ; X86-BMI2-NEXT: movb {{[0-9]+}}(%esp), %cl
110 ; X86-BMI2-NEXT: shrxl %ecx, %eax, %eax
[all …]
Dclear-highbits.ll5 …-mattr=+bmi,+tbm,+bmi2 < %s | FileCheck %s --check-prefixes=CHECK,X86,BMI2,X86-BMI2,FALLBACK3,X86-…
6 …-mattr=+bmi,-tbm,+bmi2 < %s | FileCheck %s --check-prefixes=CHECK,X86,BMI2,X86-BMI2,FALLBACK4,X86-…
10 …-mattr=+bmi,+tbm,+bmi2 < %s | FileCheck %s --check-prefixes=CHECK,X64,BMI2,X64-BMI2,FALLBACK3,X64-…
11 …-mattr=+bmi,-tbm,+bmi2 < %s | FileCheck %s --check-prefixes=CHECK,X64,BMI2,X64-BMI2,FALLBACK4,X64-…
16 ; are equivalent, but we prefer the second variant if we have BMI2.
18 ; We do not test the variant where y = (32 - z), because that is BMI2's BZHI.
107 ; X86-BMI2-LABEL: clear_highbits16_c0:
108 ; X86-BMI2: # %bb.0:
109 ; X86-BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
110 ; X86-BMI2-NEXT: shlxl %eax, {{[0-9]+}}(%esp), %ecx
[all …]
Dshift-bmi2.ll2 ; RUN: llc -mtriple=i386-unknown-unknown -mcpu=core-avx2 < %s | FileCheck --check-prefix=BMI2 %s
6 ; BMI2-LABEL: shl32:
7 ; BMI2: # %bb.0:
8 ; BMI2-NEXT: movb {{[0-9]+}}(%esp), %al
9 ; BMI2-NEXT: shlxl %eax, {{[0-9]+}}(%esp), %eax
10 ; BMI2-NEXT: retl
21 ; BMI2-LABEL: shl32i:
22 ; BMI2: # %bb.0:
23 ; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
24 ; BMI2-NEXT: shll $5, %eax
[all …]
Drot32.ll4 …RUN: llc < %s -mtriple=i686-- -mcpu=core-avx2 | FileCheck %s --check-prefix=ALL --check-prefix=BMI2
81 ; BMI2-LABEL: xfoo:
82 ; BMI2: # %bb.0: # %entry
83 ; BMI2-NEXT: rorxl $25, {{[0-9]+}}(%esp), %eax
84 ; BMI2-NEXT: retl
107 ; BMI2-LABEL: xfoop:
108 ; BMI2: # %bb.0: # %entry
109 ; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax
110 ; BMI2-NEXT: rorxl $25, (%eax), %eax
111 ; BMI2-NEXT: retl
[all …]
Drot64.ll4 …N: llc < %s -mtriple=x86_64-- -mcpu=core-avx2 | FileCheck %s --check-prefix=ALL --check-prefix=BMI2
79 ; BMI2-LABEL: xfoo:
80 ; BMI2: # %bb.0: # %entry
81 ; BMI2-NEXT: rorxq $57, %rdi, %rax
82 ; BMI2-NEXT: retq
103 ; BMI2-LABEL: xfoop:
104 ; BMI2: # %bb.0: # %entry
105 ; BMI2-NEXT: rorxq $57, (%rdi), %rax
106 ; BMI2-NEXT: retq
141 ; BMI2-LABEL: xun:
[all …]
Dbmi-x86_64.ll3 …c < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+bmi2 | FileCheck %s --check-prefixes=CHECK,BMI2
Dbmi.ll3 …iple=i686-unknown-unknown -mattr=+bmi,+bmi2 | FileCheck %s --check-prefixes=CHECK,X86,BMI2,X86-BMI2
5 …le=x86_64-unknown-unknown -mattr=+bmi,+bmi2 | FileCheck %s --check-prefixes=CHECK,X64,BMI2,X64-BMI2
/external/llvm/test/CodeGen/X86/
Dshift-bmi2.ll1 ; RUN: llc -mtriple=i386-unknown-unknown -mcpu=core-avx2 < %s | FileCheck --check-prefix=BMI2 %s
7 ; BMI2: shl32
8 ; BMI2: shlxl
9 ; BMI2: ret
19 ; BMI2: shl32i
20 ; BMI2-NOT: shlxl
21 ; BMI2: ret
32 ; BMI2: shl32p
33 ; BMI2: shlxl %{{.+}}, ({{.+}}), %{{.+}}
34 ; BMI2: ret
[all …]
Drot64.ll6 ; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s --check-prefix=BMI2
46 ; BMI2-LABEL: xfoo:
47 ; BMI2: rorxq $57
56 ; BMI2-LABEL: xfoop:
57 ; BMI2: rorxq $57, ({{.+}}), %{{.+}}
75 ; BMI2-LABEL: xun:
76 ; BMI2: rorxq $7
85 ; BMI2-LABEL: xunp:
86 ; BMI2: rorxq $7, ({{.+}}), %{{.+}}
Drot32.ll2 ; RUN: llc < %s -march=x86 -mcpu=core-avx2 | FileCheck %s --check-prefix=BMI2
52 ; BMI2-LABEL: xfoo:
53 ; BMI2: rorxl $25
62 ; BMI2-LABEL: xfoop:
63 ; BMI2: rorxl $25, ({{.+}}), %{{.+}}
85 ; BMI2-LABEL: xun:
86 ; BMI2: rorxl $7
95 ; BMI2-LABEL: xunp:
96 ; BMI2: rorxl $7, ({{.+}}), %{{.+}}
/external/skia/src/core/
DSkCpu.h26 BMI2 = 1 << 11, enumerator
28 HSW = AVX2 | BMI1 | BMI2 | F16C | FMA,
DSkCpu.cpp57 if (abcd[1] & (1<<8)) { features |= SkCpu::BMI2; } in read_cpu_features()
/external/skqp/src/core/
DSkCpu.h26 BMI2 = 1 << 11, enumerator
28 HSW = AVX2 | BMI1 | BMI2 | F16C | FMA,
DSkCpu.cpp57 if (abcd[1] & (1<<8)) { features |= SkCpu::BMI2; } in read_cpu_features()
/external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/
DJitManager.h72 bool BMI2(void) { return bForceAVX ? 0 : InstructionSet::BMI2(); } in BMI2() function
/external/tensorflow/tensorflow/core/platform/
Dcpu_info.h86 BMI2 = 23, enumerator
Dcpu_info.cc225 case BMI2: return cpuid->have_bmi2_; in TestFeature()
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/
Disa.hpp81 bool BMI2(void) { return CPU_Rep.f_7_EBX_[8]; } in BMI2() function in InstructionSet
/external/v8/src/x64/
Dassembler-x64.cc99 if (cpu.has_bmi2() && FLAG_enable_bmi2) supported_ |= 1u << BMI2; in ProbeImpl()
119 CpuFeatures::IsSupported(BMI1), CpuFeatures::IsSupported(BMI2), in PrintFeatures()
4552 DCHECK(IsEnabled(BMI2)); in bmi2q()
4561 DCHECK(IsEnabled(BMI2)); in bmi2q()
4571 DCHECK(IsEnabled(BMI2)); in bmi2l()
4580 DCHECK(IsEnabled(BMI2)); in bmi2l()
4589 DCHECK(IsEnabled(BMI2)); in rorxq()
4600 DCHECK(IsEnabled(BMI2)); in rorxq()
4612 DCHECK(IsEnabled(BMI2)); in rorxl()
4623 DCHECK(IsEnabled(BMI2)); in rorxl()
/external/v8/src/ia32/
Dassembler-ia32.cc147 if (cpu.has_bmi2() && FLAG_enable_bmi2) supported_ |= 1u << BMI2; in ProbeImpl()
166 CpuFeatures::IsSupported(BMI2), CpuFeatures::IsSupported(LZCNT), in PrintFeatures()
3087 DCHECK(IsEnabled(BMI2)); in bmi2()
3095 DCHECK(IsEnabled(BMI2)); in rorx()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ScheduleSLM.td137 // BMI1 BEXTR, BMI2 BZHI
DX86ScheduleBtVer2.td203 // BMI1 BEXTR, BMI2 BZHI
/external/v8/src/
Dglobals.h803 BMI2, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DSpeculativeLoadHardening.md612 and then shifting right by at least the number of original bits using the BMI2
753 Starting with the BMI2 x86 instruction set extensions available on Haswell and
1042 ThinLTO and PGO. All were built with `-march=haswell` to give access to BMI2
/external/llvm/lib/Target/X86/
DX86.td185 "Support BMI2 instructions">;

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