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Searched refs:COMPUTE_PGM_RSRC2 (Results 1 – 9 of 9) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DAMDHSAKernelDescriptor.h98 #define COMPUTE_PGM_RSRC2(NAME, SHIFT, WIDTH) \ macro
101 COMPUTE_PGM_RSRC2(ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, 0, 1), enumerator
102 COMPUTE_PGM_RSRC2(USER_SGPR_COUNT, 1, 5), enumerator
103 COMPUTE_PGM_RSRC2(ENABLE_TRAP_HANDLER, 6, 1), enumerator
104 COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_X, 7, 1), enumerator
105 COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_Y, 8, 1), enumerator
106 COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_ID_Z, 9, 1), enumerator
107 COMPUTE_PGM_RSRC2(ENABLE_SGPR_WORKGROUP_INFO, 10, 1), enumerator
108 COMPUTE_PGM_RSRC2(ENABLE_VGPR_WORKITEM_ID, 11, 2), enumerator
109 COMPUTE_PGM_RSRC2(ENABLE_EXCEPTION_ADDRESS_WATCH, 13, 1), enumerator
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.workgroup.id.ll30 ; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
31 ; ALL-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
32 ; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
33 ; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
34 ; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
35 ; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
58 ; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
59 ; ALL-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
60 ; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
61 ; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
[all …]
Damdgcn.work-item-intrinsics.ll26 ; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
27 ; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
28 ; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
29 ; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
30 ; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
42 ; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
54 ; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
55 ; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
56 ; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
57 ; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
[all …]
Damdgpu.work-item-intrinsics.deprecated.ll166 ; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
167 ; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
168 ; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
169 ; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
170 ; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
182 ; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
194 ; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
195 ; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
196 ; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
197 ; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.workgroup.id.ll31 ; CO-V2: COMPUTE_PGM_RSRC2:USER_SGPR: 6
32 ; ALL-NOCO-V2: COMPUTE_PGM_RSRC2:USER_SGPR: 2
33 ; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
34 ; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
35 ; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
36 ; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
58 ; CO-V2: COMPUTE_PGM_RSRC2:USER_SGPR: 6
59 ; ALL-NOCO-V2: COMPUTE_PGM_RSRC2:USER_SGPR: 2
60 ; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
61 ; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
[all …]
Damdgpu.work-item-intrinsics.deprecated.ll151 ; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
152 ; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
153 ; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
154 ; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
155 ; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
167 ; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
179 ; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
180 ; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
181 ; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
182 ; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
[all …]
Dhsa-func.ll53 ; HSA-NOT: COMPUTE_PGM_RSRC2
Dtrap.ll36 ; NO-HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUUsage.rst1647 447:416 4 bytes COMPUTE_PGM_RSRC2 Compute Shader (CS)
1650 ``COMPUTE_PGM_RSRC2``
1922 ``COMPUTE_PGM_RSRC2.SCRATCH_EN``.
1930 ``COMPUTE_PGM_RSRC2.USER_SGPR``.
1934 ``COMPUTE_PGM_RSRC2.TRAP_PRESENT``,
1945 ``COMPUTE_PGM_RSRC2.TGID_X_EN``.
1953 ``COMPUTE_PGM_RSRC2.TGID_Y_EN``.
1961 ``COMPUTE_PGM_RSRC2.TGID_Z_EN``.
1968 ``COMPUTE_PGM_RSRC2.TGID_SIZE_EN``.
1976 ``COMPUTE_PGM_RSRC2.TIDIG_CMP_CNT``.
[all …]