| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 347 DDIVU = 50, enumerator
580 latency = Latency::DDIVU; in DdivuLatency()
582 latency = Latency::DDIVU + Latency::MFLO; in DdivuLatency()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 515 DDIVU = ((3U << 3) + 7), enumerator
1332 FunctionFieldToBitNumber(DIVU) | FunctionFieldToBitNumber(DDIVU) |
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| D | disasm-mips64.cc | 1610 case DDIVU: // @Mips64r6 == D_DIV_MOD_U. in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips64.cc | 2051 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIVU); in ddivu()
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| D | simulator-mips64.cc | 3977 case DDIVU: in DecodeTypeRegisterSPECIAL()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64r6InstrInfo.td | 110 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
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| D | MipsISelLowering.cpp | 1065 case Mips::DDIVU: in EmitInstrWithCustomInserter()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips64r6InstrInfo.td | 140 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
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| D | MipsISelLowering.cpp | 1376 case Mips::DDIVU: in EmitInstrWithCustomInserter()
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_common.c | 135 #define DDIVU (HI(0) | LO(31)) macro
1099 …FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? DDIVU : DDIV) | S(SLJIT_R0) | T(SLJIT_R1… in sljit_emit_op0()
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 554 33577795U, // DDIVU
2268 0U, // DDIVU
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| D | MipsGenDisassemblerTables.inc | 3737 /* 414 */ MCD_OPC_Decode, 153, 4, 201, 1, // Opcode: DDIVU
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 1187 UINT64_C(159), // DDIVU
4416 case Mips::DDIVU:
8913 Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DDIVU = 1174
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| D | MipsGenAsmWriter.inc | 2402 268459698U, // DDIVU
5033 0U, // DDIVU
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| D | MipsGenFastISel.inc | 2514 return fastEmitInst_rr(Mips::DDIVU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
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| D | MipsGenInstrInfo.inc | 1189 DDIVU = 1174,
5234 …UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1174 = DDIVU
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| D | MipsGenGlobalISel.inc | 1711 …// (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIVU:{ *:[i64] }…
1712 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIVU,
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| D | MipsGenDisassemblerTables.inc | 6285 /* 474 */ MCD::OPC_Decode, 150, 9, 12, // Opcode: DDIVU
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| D | MipsGenAsmMatcher.inc | 5929 …{ 3153 /* ddivu */, Mips::DDIVU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_…
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| D | MipsGenDAGISel.inc | 26999 /* 50748*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DDIVU), 0,
27002 // Dst: (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2021 case Mips::DDIVU: in processInstruction()
|