Searched refs:DINSM (Results 1 – 21 of 21) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/instverify/ |
| D | dinsm-pos.mir | 45 %1 = DINSM %0, 65, 5
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| D | dinsm-pos-size.mir | 45 %1 = DINSM %0, 20, 50
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| D | dinsm-size.mir | 45 %1 = DINSM %0, 31, 67
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 581 DINSM = ((0U << 3) + 5), enumerator
1776 case DINSM: in InstructionType()
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| D | disasm-mips64.cc | 1762 case DINSM: { in DecodeTypeRegisterSPECIAL3()
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| D | assembler-mips64.cc | 2866 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1 - 32, pos, DINSM); in dinsm_()
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| D | simulator-mips64.cc | 4225 case DINSM: { // Mips64r2 instruction. in DecodeTypeRegisterSPECIAL3()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 757 case Mips::DINSM: in verifyInstruction()
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| D | Mips64InstrInfo.td | 390 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64,
954 (DINSM GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos,
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| D | MipsSEISelDAGToDAG.cpp | 961 Opcode = Mips::DINSM; in trySelect()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 117 InstIn.setOpcode(Mips::DINSM); in LowerDins()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 326 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm5_inssize_plus1>,
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 562 1107321635U, // DINSM
2276 5U, // DINSM
4845 // ALIGN, CINS, CINS32, DALIGN, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, D...
4859 // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD...
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| D | MipsGenDisassemblerTables.inc | 4538 /* 2067 */ MCD_OPC_Decode, 161, 4, 248, 1, // Opcode: DINSM
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1116 case Mips::DINSM: in DecodeDINS()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 2412 268458283U, // DINSM
5043 3652U, // DINSM
7115 // DINSM
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| D | MipsGenMCCodeEmitter.inc | 1197 UINT64_C(2080374789), // DINSM
5823 case Mips::DINSM:
8923 Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DINSM = 1184
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| D | MipsGenAsmMatcher.inc | 5945 …{ 3185 /* dins */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__Const…
5948 …{ 3190 /* dinsm */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__Cons…
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| D | MipsGenInstrInfo.inc | 1199 DINSM = 1184,
5244 …odeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1184 = DINSM
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| D | MipsGenDisassemblerTables.inc | 7012 /* 1067 */ MCD::OPC_Decode, 160, 9, 245, 2, // Opcode: DINSM
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5261 case Mips::DINSM: in checkTargetMatchPredicate()
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