Searched refs:DINSU (Results 1 – 21 of 21) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/instverify/ |
| D | dinsu-pos-size.mir | 45 %1 = DINSU %0, 50, 20
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| D | dinsu-size.mir | 45 %1 = DINSU %0, 33, 67
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| D | dinsu-pos.mir | 45 %1 = DINSU %0, 65, 5
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 582 DINSU = ((0U << 3) + 6), enumerator
1777 case DINSU: in InstructionType()
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| D | disasm-mips64.cc | 1766 case DINSU: { in DecodeTypeRegisterSPECIAL3()
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| D | assembler-mips64.cc | 2873 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1 - 32, pos - 32, DINSU); in dinsu_()
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| D | simulator-mips64.cc | 4240 case DINSU: { // Mips64r2 instruction. in DecodeTypeRegisterSPECIAL3()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 963 Opcode = Mips::DINSU; in trySelect()
1269 Res = CurDAG->getMachineNode(Mips::DINSU, DL, MVT::i64, Ops); in trySelect()
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| D | MipsInstrInfo.cpp | 764 case Mips::DINSU: in verifyInstruction()
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| D | Mips64InstrInfo.td | 387 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1,
957 (DINSU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos,
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 111 InstIn.setOpcode(Mips::DINSU); in LowerDins()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 324 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1>,
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 563 1107321673U, // DINSU
2277 5U, // DINSU
4845 // ALIGN, CINS, CINS32, DALIGN, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, D...
4859 // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD...
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| D | MipsGenDisassemblerTables.inc | 4541 /* 2080 */ MCD_OPC_Decode, 162, 4, 248, 1, // Opcode: DINSU
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1120 case Mips::DINSU: in DecodeDINS()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 2413 268459652U, // DINSU
5044 286U, // DINSU
7019 // DEXTU, DINSU
7070 // DINSU
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| D | MipsGenMCCodeEmitter.inc | 1198 UINT64_C(2080374790), // DINSU
5824 case Mips::DINSU:
8924 Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DINSU = 1185
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| D | MipsGenAsmMatcher.inc | 5946 …{ 3185 /* dins */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__Cons…
5949 …{ 3196 /* dinsu */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__Con…
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| D | MipsGenInstrInfo.inc | 1200 DINSU = 1185,
5245 …odeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1185 = DINSU
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| D | MipsGenDisassemblerTables.inc | 7015 /* 1082 */ MCD::OPC_Decode, 161, 9, 245, 2, // Opcode: DINSU
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5262 case Mips::DINSU: { in checkTargetMatchPredicate()
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