| /external/u-boot/arch/arm/include/asm/ |
| D | barriers.h | 34 #define DSB asm volatile ("dsb sy" : : : "memory") macro
38 #define DSB CP15DSB macro
42 #define DSB CP15DSB macro
47 #define dsb() DSB
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | invalid-DSB-arm.txt | 3 # Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26)
12 # See also A8.6.42 DSB
15 # system DSB operation, but software must not rely on this behavior.
|
| D | invalid-DMB-thumb.txt | 12 # See also A8.6.42 DSB
15 # system DSB operation, but software must not rely on this behavior.
|
| /external/libavc/common/arm/ |
| D | ih264_arm_memory_barrier.s | 45 @* Description : Adds DSB
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | invalid-barrier.s | 14 @ DSB
|
| D | basic-arm-instructions-v8.s | 37 @ DSB (v8 barriers)
|
| D | basic-thumb2-instructions-v8.s | 77 @ DSB (ARMv8-only barriers)
|
| /external/llvm/test/MC/ARM/ |
| D | invalid-barrier.s | 14 @ DSB
|
| D | basic-arm-instructions-v8.s | 37 @ DSB (v8 barriers)
|
| D | basic-thumb2-instructions-v8.s | 67 @ DSB (ARMv8-only barriers)
|
| /external/u-boot/arch/arm/mach-imx/ |
| D | cache.c | 35 DSB; in enable_ca7_smp()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | intrinsics-memory-barrier.ll | 27 ; Similarly for DSB.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | intrinsics-memory-barrier.ll | 31 ; Similarly for DSB.
|
| /external/llvm/test/CodeGen/ARM/ |
| D | intrinsics-memory-barrier.ll | 27 ; Similarly for DSB.
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | intrinsics-memory-barrier.ll | 31 ; Similarly for DSB.
|
| /external/u-boot/arch/arm/cpu/armv7/ |
| D | start.S | 102 mcr p15, 0, r0, c7, c10, 4 @ DSB
147 mcr p15, 0, r0, c7, c10, 4 @ DSB
|
| /external/u-boot/arch/arm/mach-omap2/omap3/ |
| D | lowlevel_init.S | 32 mcr p15, 0, r0, c7, c10, 4 @ DSB
|
| /external/walt/hardware/enclosure/ |
| D | WALT_recessed_enclosure.stl | 28 …@���@DSB�>�@��L@��� �6�J�����DSB�>�@��L@��SB�t�@���@DSB�>�@���@���P���P�����DSB�>�@��L@DSB�…
93 …|B���@DSBűB��L@���P���P?����DSBűB��L@��RB�|B���@DSBűB���@��� �6�J?����DSBűB��L@DSBűB…
557 …AB_��?���@�������������??bAB_��?���@P;KBE��@���@L�AB���@���@�������������?DSB�>�@���@[^YB�KA���@…
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 292 // SLREX,DMB,DSB
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 294 // SLREX,DMB,DSB
|
| D | AArch64SchedFalkorDetails.td | 1245 def : InstRW<[FalkorWr_1LD_0cyc], (instrs CLREX, DMB, DSB)>;
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 774 DSB = MemBarrierFixed | 0x00000000, enumerator
|
| D | disasm-arm64.cc | 1262 case DSB: { in VisitSystem()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmWriter.inc | 1106 66767U, // DSB
4326 0U, // DSB
7049 // DMB, DSB
9328 case ARM::DSB:
9334 // (DSB 12)
|
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 755 DSB = MemBarrierFixed | 0x00000000, enumerator
|