| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 122 def DSLLV : LogicR_shift_rotate_reg64<0x24, 0x00, "dsllv", shl>;
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 149 def DSLLV : StdMMR6Rel, shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
575 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
654 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 167 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
744 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
942 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
951 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>,
|
| /external/v8/src/mips64/ |
| D | constants-mips64.h | 503 DSLLV = ((2U << 3) + 4), enumerator
1324 FunctionFieldToBitNumber(SLLV) | FunctionFieldToBitNumber(DSLLV) |
|
| D | disasm-mips64.cc | 1490 case DSLLV: in DecodeTypeRegisterSPECIAL()
|
| D | assembler-mips64.cc | 2171 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSLLV); in dsllv()
|
| D | simulator-mips64.cc | 3762 case DSLLV: in DecodeTypeRegisterSPECIAL()
|
| /external/u-boot/arch/sh/include/asm/ |
| D | cpu_sh7722.h | 845 #define DSLLV 0xA454C0F8 macro
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 491 EMIT_SHIFT(DSLL, DSLL32, SLL, DSLLV, SLLV); in emit_single_op()
|
| D | sljitNativeMIPS_common.c | 143 #define DSLLV (HI(0) | LO(20)) macro
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3552 SecondShift = Mips::DSLLV; in expandDRotation()
3555 FirstShift = Mips::DSLLV; in expandDRotation()
|
| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 636 33577893U, // DSLLV
2350 0U, // DSLLV
|
| D | MipsGenDisassemblerTables.inc | 4096 /* 24 */ MCD_OPC_Decode, 235, 4, 230, 1, // Opcode: DSLLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4574 SecondShift = Mips::DSLLV; in expandDRotation()
4577 FirstShift = Mips::DSLLV; in expandDRotation()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 1295 UINT64_C(20), // DSLLV
4619 case Mips::DSLLV:
9021 Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSLLV = 1282
|
| D | MipsGenAsmWriter.inc | 2510 268459796U, // DSLLV
5141 0U, // DSLLV
|
| D | MipsGenGlobalISel.inc | 12520 …} GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSLLV:{ *:[i64] } GPR64:…
12526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLLV,
12538 …// (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSLLV:{ *:[i64] } …
12539 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSLLV,
|
| D | MipsGenAsmMatcher.inc | 6103 …{ 3839 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, Feature_H…
6105 …{ 3839 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_H…
6109 …{ 3851 /* dsllv */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_…
|
| D | MipsGenDAGISel.inc | 20294 /* 37572*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSLLV), 0,
20297 …// Dst: (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$r…
20323 /* 37626*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSLLV), 0,
20326 // Dst: (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
|
| D | MipsGenInstrInfo.inc | 1297 DSLLV = 1282,
5342 …2, 3, 1, 4, 117, 0, 0x1ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1282 = DSLLV
|
| D | MipsGenDisassemblerTables.inc | 6824 /* 99 */ MCD::OPC_Decode, 130, 10, 234, 2, // Opcode: DSLLV
|