| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 75 case Mips::DSRA: in LowerLargeShift()
198 case Mips::DSRA: in encodeInstruction()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 118 def DSRA : LogicR_shift_rotate_imm64<0x3b, 0x00, "dsra", sra, immZExt5>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 83 case Mips::DSRA: in LowerLargeShift()
167 case Mips::DSRA: in encodeInstruction()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 544 DSRA = ((7U << 3) + 3), enumerator
1323 FunctionFieldToBitNumber(DSRA) | FunctionFieldToBitNumber(DSRA32) |
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| D | disasm-mips64.cc | 1481 case DSRA: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips64.cc | 2208 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRA); in dsra()
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| D | simulator-mips64.cc | 3753 case DSRA: in DecodeTypeRegisterSPECIAL()
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 499 EMIT_SHIFT(DSRA, DSRA32, SRA, DSRAV, SRAV); in emit_single_op()
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| D | sljitNativeMIPS_common.c | 144 #define DSRA (HI(0) | LO(59)) macro
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 146 def DSRA : StdMMR6Rel, shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 164 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra,
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 637 1107312982U, // DSRA
2351 0U, // DSRA
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| D | MipsGenDisassemblerTables.inc | 4156 /* 299 */ MCD_OPC_Decode, 236, 4, 232, 1, // Opcode: DSRA
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 2511 268452552U, // DSRA
5142 12U, // DSRA
6980 // BCLRI_D, BNEGI_D, BSETI_D, DEXT, DEXT64_32, DINS, DROTR, DSLL, DSRA, D...
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| D | MipsGenMCCodeEmitter.inc | 1296 UINT64_C(59), // DSRA
4674 case Mips::DSRA:
9022 Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSRA = 1283
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| D | MipsGenFastISel.inc | 3738 return fastEmitInst_ri(Mips::DSRA, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
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| D | MipsGenAsmMatcher.inc | 6110 …{ 3857 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Featur…
6112 …{ 3857 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Featur…
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| D | MipsGenInstrInfo.inc | 1298 DSRA = 1283,
5343 …283, 3, 1, 4, 118, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1283 = DSRA
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| D | MipsGenGlobalISel.inc | 12979 …:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRA:{ *:[i64] } GPR64Op…
12980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRA,
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| D | MipsGenDisassemblerTables.inc | 6884 /* 413 */ MCD::OPC_Decode, 131, 10, 236, 2, // Opcode: DSRA
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| D | MipsGenDAGISel.inc | 21378 /* 39561*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRA), 0,
21381 // Dst: (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
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