| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 123 def DSRLV : LogicR_shift_rotate_reg64<0x26, 0x00, "dsrlv", srl>;
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 153 def DSRLV : StdMMR6Rel, shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
577 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
696 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 171 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
747 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
945 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
948 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>,
|
| /external/v8/src/mips64/ |
| D | constants-mips64.h | 505 DSRLV = ((2U << 3) + 6), enumerator
1325 FunctionFieldToBitNumber(SRLV) | FunctionFieldToBitNumber(DSRLV) |
|
| D | disasm-mips64.cc | 1500 case DSRLV: in DecodeTypeRegisterSPECIAL()
|
| D | assembler-mips64.cc | 2181 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRLV); in dsrlv()
2202 | (rd.code() << kRdShift) | (1 << kSaShift) | DSRLV; in drotrv()
|
| D | simulator-mips64.cc | 3780 case DSRLV: in DecodeTypeRegisterSPECIAL()
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 495 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV); in emit_single_op()
|
| D | sljitNativeMIPS_common.c | 149 #define DSRLV (HI(0) | LO(22)) macro
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3551 FirstShift = Mips::DSRLV; in expandDRotation()
3556 SecondShift = Mips::DSRLV; in expandDRotation()
|
| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 642 33577900U, // DSRLV
2356 0U, // DSRLV
|
| D | MipsGenDisassemblerTables.inc | 4101 /* 44 */ MCD_OPC_Decode, 241, 4, 230, 1, // Opcode: DSRLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4573 FirstShift = Mips::DSRLV; in expandDRotation()
4578 SecondShift = Mips::DSRLV; in expandDRotation()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 1301 UINT64_C(22), // DSRLV
4621 case Mips::DSRLV:
9027 Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSRLV = 1288
|
| D | MipsGenAsmWriter.inc | 2516 268459803U, // DSRLV
5147 0U, // DSRLV
|
| D | MipsGenGlobalISel.inc | 12768 …} GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRLV:{ *:[i64] } GPR64:…
12774 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRLV,
12786 …// (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRLV:{ *:[i64] } …
12787 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRLV,
|
| D | MipsGenAsmMatcher.inc | 6116 …{ 3875 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, Feature_H…
6118 …{ 3875 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_H…
6122 …{ 3887 /* dsrlv */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_…
|
| D | MipsGenDAGISel.inc | 20859 /* 38610*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRLV), 0,
20862 …// Dst: (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$r…
20888 /* 38664*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRLV), 0,
20891 // Dst: (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
|
| D | MipsGenInstrInfo.inc | 1303 DSRLV = 1288,
5348 …8, 3, 1, 4, 123, 0, 0x1ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1288 = DSRLV
|
| D | MipsGenDisassemblerTables.inc | 6829 /* 122 */ MCD::OPC_Decode, 136, 10, 234, 2, // Opcode: DSRLV
|