| /external/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 128 unsigned DefIdx = 0; in findDefIdx() local
132 ++DefIdx; in findDefIdx()
134 return DefIdx; in findDefIdx()
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
189 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
192 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
214 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
228 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
229 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
232 STI->getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
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| D | PeepholeOptimizer.cpp | 296 unsigned DefIdx; member in __anond69149540111::ValueTracker
354 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg), in ValueTracker()
358 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
369 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg, in ValueTracker() argument
373 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg), in ValueTracker()
375 assert(DefIdx < Def->getDesc().getNumDefs() && in ValueTracker()
376 Def->getOperand(DefIdx).isReg() && "Invalid definition"); in ValueTracker()
377 Reg = Def->getOperand(DefIdx).getReg(); in ValueTracker()
1672 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1691 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromBitcast()
[all …]
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| D | TargetInstrInfo.cpp | 982 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
992 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
994 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1056 unsigned DefIdx) const { in hasLowDefLatency()
1062 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1070 unsigned DefIdx, in getOperandLatency() argument
1075 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1096 unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const { in computeOperandLatency() argument
1106 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, *UseMI, UseIdx); in computeOperandLatency()
1109 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx); in computeOperandLatency()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 182 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
186 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
188 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
196 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
203 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
208 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
218 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
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| D | MCSubtargetInfo.h | 130 unsigned DefIdx) const { in getWriteLatencyEntry() argument
131 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
134 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInstrItineraries.h | 199 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
203 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
205 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
213 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
220 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
225 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
235 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 186 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
190 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
192 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
200 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
207 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
212 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
222 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
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| D | MCSubtargetInfo.h | 129 unsigned DefIdx) const { in getWriteLatencyEntry() argument
130 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
133 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
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| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetInstrInfo.cpp | 66 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency() argument
73 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
78 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
88 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
90 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
115 unsigned DefIdx) const { in hasLowDefLatency()
120 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 55 const MachineInstr &MI, unsigned DefIdx,
68 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
84 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
282 const MachineInstr &DefMI, unsigned DefIdx,
286 SDNode *DefNode, unsigned DefIdx,
309 unsigned DefIdx, unsigned DefAlign) const;
313 unsigned DefIdx, unsigned DefAlign) const;
324 unsigned DefIdx, unsigned DefAlign,
329 const MachineInstr &DefMI, unsigned DefIdx,
346 const MachineInstr &DefMI, unsigned DefIdx,
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizationArtifactCombiner.h | 164 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; in tryCombineMerges() local
165 ++j, ++DefIdx) in tryCombineMerges()
166 DstRegs.push_back(MI.getOperand(DefIdx).getReg()); in tryCombineMerges()
184 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineMerges() local
186 for (unsigned j = 0, Idx = NumRegs * DefIdx + 1; j < NumRegs; in tryCombineMerges()
190 Builder.buildMerge(MI.getOperand(DefIdx).getReg(), Regs); in tryCombineMerges()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 60 const MachineInstr &MI, unsigned DefIdx,
73 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
89 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
313 const MachineInstr &DefMI, unsigned DefIdx,
317 SDNode *DefNode, unsigned DefIdx,
340 unsigned DefIdx, unsigned DefAlign) const;
344 unsigned DefIdx, unsigned DefAlign) const;
355 unsigned DefIdx, unsigned DefAlign,
360 const MachineInstr &DefMI, unsigned DefIdx,
377 const MachineInstr &DefMI, unsigned DefIdx,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 159 unsigned DefIdx = 0; in findDefIdx() local
163 ++DefIdx; in findDefIdx()
165 return DefIdx; in findDefIdx()
219 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
220 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
223 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
245 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
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| D | TargetInstrInfo.cpp | 1041 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
1051 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1053 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1115 unsigned DefIdx) const { in hasLowDefLatency()
1121 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1129 unsigned DefIdx, in getOperandLatency() argument
1134 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1154 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs() argument
1160 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs); in getRegSequenceInputs()
1164 assert(DefIdx == 0 && "REG_SEQUENCE only has one def"); in getRegSequenceInputs()
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| D | PeepholeOptimizer.cpp | 370 unsigned DefIdx = 0; member in __anon5d64f7ac0111::ValueTracker
424 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
1814 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1835 const MachineOperand DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast()
1842 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1874 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
1897 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs)) in getNextSourceFromRegSequence()
1923 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
1936 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg)) in getNextSourceFromInsertSubreg()
1952 const MachineOperand &MODef = Def->getOperand(DefIdx); in getNextSourceFromInsertSubreg()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 209 const MachineInstr *DefMI, unsigned DefIdx,
213 SDNode *DefNode, unsigned DefIdx,
225 unsigned DefIdx, unsigned DefAlign) const;
229 unsigned DefIdx, unsigned DefAlign) const;
240 unsigned DefIdx, unsigned DefAlign,
252 const MachineInstr *DefMI, unsigned DefIdx,
255 const MachineInstr *DefMI, unsigned DefIdx) const;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/ |
| D | MCSchedule.cpp | 44 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
45 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
48 STI.getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 391 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
409 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
429 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
934 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
948 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs() argument
962 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs() argument
1221 SDNode *DefNode, unsigned DefIdx,
1233 const MachineInstr &DefMI, unsigned DefIdx,
1249 const MachineInstr &DefMI, unsigned DefIdx,
1282 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 464 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
482 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
502 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
1028 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
1042 unsigned DefIdx, in getExtractSubregLikeInputs() argument
1056 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs() argument
1330 SDNode *DefNode, unsigned DefIdx,
1342 const MachineInstr &DefMI, unsigned DefIdx,
1375 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
1385 unsigned DefIdx) const;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 119 const MachineInstr &DefMI, unsigned DefIdx,
123 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
125 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
131 unsigned DefIdx) const override { in hasLowDefLatency() argument
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| D | PPCVSXSwapRemoval.cpp | 617 int DefIdx = SwapMap[DefMI]; in formWebs() local
618 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
621 DEBUG(dbgs() << format("Unioning %d with %d\n", SwapVector[DefIdx].VSEId, in formWebs()
696 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
698 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
699 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
705 DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
771 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
772 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 624 int DefIdx = SwapMap[DefMI]; in formWebs() local
625 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
629 SwapVector[DefIdx].VSEId, in formWebs()
705 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
707 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
708 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
714 LLVM_DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
781 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
782 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 127 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); in constrainSelectedInstRegOperands() local
128 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx)) in constrainSelectedInstRegOperands()
129 I.tieOperands(DefIdx, OpI); in constrainSelectedInstRegOperands()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | LiveRangeEdit.cpp | 122 SlotIndex DefIdx; in canRematerializeAt() local
124 DefIdx = lis.getInstructionIndex(RM.OrigMI); in canRematerializeAt()
126 DefIdx = RM.ParentVNI->def; in canRematerializeAt()
127 RM.OrigMI = lis.getInstructionFromIndex(DefIdx); in canRematerializeAt()
136 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx, lis)) in canRematerializeAt()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 507 DefIdx = 0; in InitNodeNumDefs()
513 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { in RegDefIter()
521 for (;DefIdx < NodeNumDefs; ++DefIdx) { in Advance()
522 if (!Node->hasAnyUseOfValue(DefIdx)) in Advance()
524 ValueType = Node->getValueType(DefIdx); in Advance()
525 ++DefIdx; in Advance()
587 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in ComputeOperandLatency() local
591 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in ComputeOperandLatency()
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