/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 518 FP16_TO_FP, FP_TO_FP16, enumerator
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 551 FP16_TO_FP, FP_TO_FP16, enumerator
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeFloatTypes.cpp | 503 return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, Op); in SoftenFloatRes_FP_ROUND() 615 return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, N->getOperand(0)); in SoftenFloatRes_FTRUNC() 757 case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes in SoftenFloatOperand() 850 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16); in SoftenFloatOp_FP_ROUND() 854 EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT; in SoftenFloatOp_FP_ROUND() 1727 return ISD::FP_TO_FP16; in GetPromotionOpcode() 1858 case ISD::FP_TO_FP16: in PromoteFloatResult()
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D | SelectionDAGDumper.cpp | 261 case ISD::FP_TO_FP16: return "fp_to_fp16"; in getOperationName()
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D | LegalizeDAG.cpp | 963 case ISD::FP_TO_FP16: in LegalizeOp() 3179 case ISD::FP_TO_FP16: in ExpandNode() 3184 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) { in ExpandNode() 3190 DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal)); in ExpandNode() 3930 case ISD::FP_TO_FP16: { in ConvertNodeToLibcall()
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D | LegalizeIntegerTypes.cpp | 117 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break; in PromoteIntegerResult() 271 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp); in PromoteIntRes_BITCAST()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeFloatTypes.cpp | 504 return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, Op); in SoftenFloatRes_FP_ROUND() 616 return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, N->getOperand(0)); in SoftenFloatRes_FTRUNC() 762 case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes in SoftenFloatOperand() 865 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16); in SoftenFloatOp_FP_ROUND() 869 EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT; in SoftenFloatOp_FP_ROUND() 1744 return ISD::FP_TO_FP16; in GetPromotionOpcode() 1876 case ISD::FP_TO_FP16: in PromoteFloatResult()
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D | SelectionDAGDumper.cpp | 304 case ISD::FP_TO_FP16: return "fp_to_fp16"; in getOperationName()
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D | LegalizeDAG.cpp | 994 case ISD::FP_TO_FP16: in LegalizeOp() 3286 case ISD::FP_TO_FP16: in ExpandNode() 3292 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) { in ExpandNode() 3298 DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal)); in ExpandNode() 4216 case ISD::FP_TO_FP16: { in ConvertNodeToLibcall()
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D | LegalizeIntegerTypes.cpp | 119 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break; in PromoteIntegerResult() 273 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp)); in PromoteIntRes_BITCAST()
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D | SelectionDAG.cpp | 3895 case ISD::FP_TO_FP16: { in getNode()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | AMDGPUISelLowering.h | 439 FP_TO_FP16, enumerator
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D | AMDGPUInstrInfo.td | 155 def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
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D | AMDGPUISelLowering.cpp | 344 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom); in AMDGPUTargetLowering() 345 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom); in AMDGPUTargetLowering() 1145 case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG); in LowerOperation() 2495 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0); in LowerFP_TO_FP16() 4083 NODE_NAME_CASE(FP_TO_FP16) in getTargetNodeName() 4203 case AMDGPUISD::FP_TO_FP16: in computeKnownBitsForTargetNode() 4316 case AMDGPUISD::FP_TO_FP16: in ComputeNumSignBitsForTargetNode()
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D | SIISelLowering.cpp | 438 setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote); in SITargetLowering() 439 AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32); in SITargetLowering() 4036 SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src); in lowerFP_ROUND()
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/external/llvm/lib/Target/X86/ |
D | X86IntrinsicsInfo.h | 1484 ISD::FP_TO_FP16, 0), 1486 ISD::FP_TO_FP16, 0), 1488 ISD::FP_TO_FP16, 0),
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D | X86InstrFragmentsSIMD.td | 560 def X86cvtps2ph : SDNode<"ISD::FP_TO_FP16",
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D | X86ISelLowering.cpp | 354 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in X86TargetLowering() 360 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in X86TargetLowering() 361 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand); in X86TargetLowering() 17244 case ISD::FP_TO_FP16: in getVectorMaskingNode()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyISelLowering.cpp | 101 setOperationAction(ISD::FP_TO_FP16, T, Expand); in WebAssemblyTargetLowering()
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/external/llvm/include/llvm/Target/ |
D | TargetSelectionDAG.td | 464 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
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/external/llvm/lib/Target/Mips/ |
D | MipsISelLowering.cpp | 375 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in MipsTargetLowering() 377 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in MipsTargetLowering()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
D | MipsISelLowering.cpp | 452 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in MipsTargetLowering() 454 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in MipsTargetLowering()
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
D | TargetSelectionDAG.td | 446 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 960 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in ARMTargetLowering() 966 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in ARMTargetLowering()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 1092 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in ARMTargetLowering() 1098 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in ARMTargetLowering()
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