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Searched refs:FP_TO_FP16 (Results 1 – 25 of 29) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h518 FP16_TO_FP, FP_TO_FP16, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h551 FP16_TO_FP, FP_TO_FP16, enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp503 return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, Op); in SoftenFloatRes_FP_ROUND()
615 return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, N->getOperand(0)); in SoftenFloatRes_FTRUNC()
757 case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes in SoftenFloatOperand()
850 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16); in SoftenFloatOp_FP_ROUND()
854 EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT; in SoftenFloatOp_FP_ROUND()
1727 return ISD::FP_TO_FP16; in GetPromotionOpcode()
1858 case ISD::FP_TO_FP16: in PromoteFloatResult()
DSelectionDAGDumper.cpp261 case ISD::FP_TO_FP16: return "fp_to_fp16"; in getOperationName()
DLegalizeDAG.cpp963 case ISD::FP_TO_FP16: in LegalizeOp()
3179 case ISD::FP_TO_FP16: in ExpandNode()
3184 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) { in ExpandNode()
3190 DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal)); in ExpandNode()
3930 case ISD::FP_TO_FP16: { in ConvertNodeToLibcall()
DLegalizeIntegerTypes.cpp117 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break; in PromoteIntegerResult()
271 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp); in PromoteIntRes_BITCAST()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp504 return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, Op); in SoftenFloatRes_FP_ROUND()
616 return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, N->getOperand(0)); in SoftenFloatRes_FTRUNC()
762 case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes in SoftenFloatOperand()
865 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16); in SoftenFloatOp_FP_ROUND()
869 EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT; in SoftenFloatOp_FP_ROUND()
1744 return ISD::FP_TO_FP16; in GetPromotionOpcode()
1876 case ISD::FP_TO_FP16: in PromoteFloatResult()
DSelectionDAGDumper.cpp304 case ISD::FP_TO_FP16: return "fp_to_fp16"; in getOperationName()
DLegalizeDAG.cpp994 case ISD::FP_TO_FP16: in LegalizeOp()
3286 case ISD::FP_TO_FP16: in ExpandNode()
3292 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) { in ExpandNode()
3298 DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal)); in ExpandNode()
4216 case ISD::FP_TO_FP16: { in ConvertNodeToLibcall()
DLegalizeIntegerTypes.cpp119 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break; in PromoteIntegerResult()
273 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp)); in PromoteIntRes_BITCAST()
DSelectionDAG.cpp3895 case ISD::FP_TO_FP16: { in getNode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h439 FP_TO_FP16, enumerator
DAMDGPUInstrInfo.td155 def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
DAMDGPUISelLowering.cpp344 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom); in AMDGPUTargetLowering()
345 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom); in AMDGPUTargetLowering()
1145 case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG); in LowerOperation()
2495 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0); in LowerFP_TO_FP16()
4083 NODE_NAME_CASE(FP_TO_FP16) in getTargetNodeName()
4203 case AMDGPUISD::FP_TO_FP16: in computeKnownBitsForTargetNode()
4316 case AMDGPUISD::FP_TO_FP16: in ComputeNumSignBitsForTargetNode()
DSIISelLowering.cpp438 setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote); in SITargetLowering()
439 AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32); in SITargetLowering()
4036 SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src); in lowerFP_ROUND()
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h1484 ISD::FP_TO_FP16, 0),
1486 ISD::FP_TO_FP16, 0),
1488 ISD::FP_TO_FP16, 0),
DX86InstrFragmentsSIMD.td560 def X86cvtps2ph : SDNode<"ISD::FP_TO_FP16",
DX86ISelLowering.cpp354 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in X86TargetLowering()
360 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in X86TargetLowering()
361 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand); in X86TargetLowering()
17244 case ISD::FP_TO_FP16: in getVectorMaskingNode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp101 setOperationAction(ISD::FP_TO_FP16, T, Expand); in WebAssemblyTargetLowering()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td464 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp375 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in MipsTargetLowering()
377 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in MipsTargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.cpp452 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in MipsTargetLowering()
454 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in MipsTargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTargetSelectionDAG.td446 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp960 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in ARMTargetLowering()
966 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in ARMTargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelLowering.cpp1092 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in ARMTargetLowering()
1098 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in ARMTargetLowering()

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