Searched refs:FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK (Results 1 – 9 of 9) sorted by relevance
48 cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in serdes_get_first_lane()79 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in get_serdes_protocol()176 cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in setup_serdes_volt()357 cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in setup_serdes_volt()408 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK, in fsl_serdes_init()
26 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in board_eth_init()88 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in fdt_update_ethernet_dt()
26 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in board_eth_init()
49 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in pfe_eth_board_init()
262 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in fdt_fixup_board_enet()304 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in board_eth_init()
182 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in fdt_fsl_fixup_of_pfe()
140 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in pfe_eth_board_init()
262 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; in board_eth_init()
268 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 macro