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Searched refs:GENX (Results 1 – 15 of 15) sorted by relevance

/external/mesa3d/src/intel/vulkan/
DgenX_gpu_memcpy.c71 anv_batch_emit(&cmd_buffer->batch, GENX(MI_COPY_MEM_MEM), cp) { in genX()
80 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_MEM), load) { in genX()
84 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), store) { in genX()
132 dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_VERTEX_BUFFERS)); in genX()
133 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, dw + 1, in genX()
134 &(struct GENX(VERTEX_BUFFER_STATE)) { in genX()
140 .MemoryObjectControlState = GENX(MOCS), in genX()
143 .VertexBufferMemoryObjectControlState = GENX(MOCS), in genX()
148 dw = anv_batch_emitn(&cmd_buffer->batch, 3, GENX(3DSTATE_VERTEX_ELEMENTS)); in genX()
149 GENX(VERTEX_ELEMENT_STATE_pack)(&cmd_buffer->batch, dw + 1, in genX()
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Dgen8_cmd_buffer.c50 struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = { in gen8_cmd_buffer_emit_viewport()
67 GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64, in gen8_cmd_buffer_emit_viewport()
74 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) { in gen8_cmd_buffer_emit_viewport()
92 struct GENX(CC_VIEWPORT) cc_viewport = { in gen8_cmd_buffer_emit_depth_viewport()
97 GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport); in gen8_cmd_buffer_emit_depth_viewport()
103 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) { in gen8_cmd_buffer_emit_depth_viewport()
126 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
135 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0), in genX()
138 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in genX()
139 lri.RegisterOffset = GENX(CACHE_MODE_0_num); in genX()
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DgenX_state.c49 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) { in gen10_emit_wa_cs_stall_flush()
69 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) { in gen10_emit_wa_lri_to_cache_mode_zero()
82 anv_pack_struct(&cache_mode_0, GENX(CACHE_MODE_0)); in gen10_emit_wa_lri_to_cache_mode_zero()
84 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in gen10_emit_wa_lri_to_cache_mode_zero()
85 lri.RegisterOffset = GENX(CACHE_MODE_0_num); in gen10_emit_wa_lri_to_cache_mode_zero()
94 GENX(MEMORY_OBJECT_CONTROL_STATE_pack)(NULL, &device->default_mocs, in genX()
95 &GENX(MOCS)); in genX()
103 anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) { in genX()
112 anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1), in genX()
118 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in genX()
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DgenX_query.c302 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_ps_depth_count()
317 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_query_availability()
339 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { in emit_zero_queries()
359 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdm) { in genX()
370 GENX(IA_VERTICES_COUNT_num),
371 GENX(IA_PRIMITIVES_COUNT_num),
372 GENX(VS_INVOCATION_COUNT_num),
373 GENX(GS_INVOCATION_COUNT_num),
374 GENX(GS_PRIMITIVES_COUNT_num),
375 GENX(CL_INVOCATION_COUNT_num),
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DgenX_pipeline.c115 GENX(3DSTATE_VERTEX_ELEMENTS)); in emit_vertex_input()
138 struct GENX(VERTEX_ELEMENT_STATE) element = { in emit_vertex_input()
141 .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) format, in emit_vertex_input()
149 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element); in emit_vertex_input()
156 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING), vfi) { in emit_vertex_input()
184 struct GENX(VERTEX_ELEMENT_STATE) element = { in emit_vertex_input()
187 .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32G32_UINT, in emit_vertex_input()
198 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + id_slot * 2], &element); in emit_vertex_input()
202 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS), sgvs) { in emit_vertex_input()
214 struct GENX(VERTEX_ELEMENT_STATE) element = { in emit_vertex_input()
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Dgen7_cmd_buffer.c164 uint32_t sf_dw[GENX(3DSTATE_SF_length)]; in genX()
165 struct GENX(3DSTATE_SF) sf = { in genX()
166 GENX(3DSTATE_SF_header), in genX()
173 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf); in genX()
182 GENX(COLOR_CALC_STATE_length) * 4, in genX()
184 struct GENX(COLOR_CALC_STATE) cc = { in genX()
192 GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc); in genX()
195 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) { in genX()
204 uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)]; in genX()
206 struct GENX(DEPTH_STENCIL_STATE) depth_stencil = { in genX()
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DgenX_cmd_buffer.c39 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in emit_lrm()
48 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in emit_lri()
58 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_REG), lrr) { in emit_lrr()
77 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
83 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) { in genX()
85 sba.GeneralStateMemoryObjectControlState = GENX(MOCS); in genX()
90 sba.SurfaceStateMemoryObjectControlState = GENX(MOCS); in genX()
95 sba.DynamicStateMemoryObjectControlState = GENX(MOCS); in genX()
99 sba.IndirectObjectMemoryObjectControlState = GENX(MOCS); in genX()
104 sba.InstructionMemoryObjectControlState = GENX(MOCS); in genX()
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DgenX_blorp_exec.c215 blorp_emit(batch, GENX(3DSTATE_VF_STATISTICS), vf) { in genX()
/external/mesa3d/src/intel/blorp/
Dblorp_genX_exec.h269 struct GENX(VERTEX_BUFFER_STATE) vb[2]; in blorp_emit_vertex_buffers()
314 const unsigned num_dwords = 1 + GENX(VERTEX_BUFFER_STATE_length) * 2; in blorp_emit_vertex_buffers()
315 uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS), num_dwords); in blorp_emit_vertex_buffers()
320 GENX(VERTEX_BUFFER_STATE_pack)(batch, dw, &vb[i]); in blorp_emit_vertex_buffers()
321 dw += GENX(VERTEX_BUFFER_STATE_length); in blorp_emit_vertex_buffers()
334 struct GENX(VERTEX_ELEMENT_STATE) ve[num_elements]; in blorp_emit_vertex_elements()
385 ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) { in blorp_emit_vertex_elements()
388 .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32G32B32A32_FLOAT, in blorp_emit_vertex_elements()
417 ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) { in blorp_emit_vertex_elements()
420 .SourceElementFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_R32G32B32_FLOAT, in blorp_emit_vertex_elements()
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/external/mesa3d/src/intel/isl/
Disl_emit_depth_stencil.c63 struct GENX(3DSTATE_DEPTH_BUFFER) db = { in isl_genX()
64 GENX(3DSTATE_DEPTH_BUFFER_header), in isl_genX()
123 struct GENX(3DSTATE_STENCIL_BUFFER) sb = { in isl_genX()
124 GENX(3DSTATE_STENCIL_BUFFER_header), in isl_genX()
149 struct GENX(3DSTATE_HIER_DEPTH_BUFFER) hiz = { in isl_genX()
150 GENX(3DSTATE_HIER_DEPTH_BUFFER_header), in isl_genX()
152 struct GENX(3DSTATE_CLEAR_PARAMS) clear = { in isl_genX()
153 GENX(3DSTATE_CLEAR_PARAMS_header), in isl_genX()
208 GENX(3DSTATE_DEPTH_BUFFER_pack)(NULL, dw, &db); in isl_genX()
209 dw += GENX(3DSTATE_DEPTH_BUFFER_length); in isl_genX()
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Disl_surface_state.c236 struct GENX(RENDER_SURFACE_STATE) s = { 0 }; in isl_genX()
271 s.SurfaceFormat = (enum GENX(SURFACE_FORMAT)) info->view->format; in isl_genX()
503 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r; in isl_genX()
504 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g; in isl_genX()
505 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b; in isl_genX()
506 s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a; in isl_genX()
669 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); in isl_genX()
696 struct GENX(RENDER_SURFACE_STATE) s = { 0, }; in isl_genX()
699 s.SurfaceFormat = (enum GENX(SURFACE_FORMAT)) info->format; in isl_genX()
749 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); in isl_genX()
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/external/mesa3d/src/intel/genxml/
Dgen_macros.h65 # define GENX(X) GEN4_##X macro
68 # define GENX(X) GEN45_##X macro
71 # define GENX(X) GEN5_##X macro
74 # define GENX(X) GEN6_##X macro
77 # define GENX(X) GEN7_##X macro
80 # define GENX(X) GEN75_##X macro
83 # define GENX(X) GEN8_##X macro
86 # define GENX(X) GEN9_##X macro
89 # define GENX(X) GEN10_##X macro
/external/mesa3d/src/mesa/drivers/dri/i965/
DgenX_state_upload.c192 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) { in genX()
231 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_OFFSET), poly) { in genX()
267 brw_batch_emit(brw, GENX(3DSTATE_LINE_STIPPLE), line) { in genX()
292 brw_batch_emit(brw, GENX(3DSTATE_DRAWING_RECTANGLE), rect) { in genX()
317 struct GENX(VERTEX_BUFFER_STATE) buf_state = { in genX()
348 GENX(VERTEX_BUFFER_STATE_pack)(brw, dw, &buf_state); in genX()
349 return dw + GENX(VERTEX_BUFFER_STATE_length); in genX()
489 brw_batch_emit(brw, GENX(3DSTATE_VF_SGVS), vfs) { in genX()
503 brw_batch_emit(brw, GENX(3DSTATE_VF_INSTANCING), vfi) { in genX()
508 brw_batch_emit(brw, GENX(3DSTATE_VF_SGVS), vfs); in genX()
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Dgen4_blorp_exec.h56 blorp_emit_dynamic(batch, GENX(VS_STATE), vs, 64, &offset) { in blorp_emit_vs_state()
78 blorp_emit_dynamic(batch, GENX(SF_STATE), sf, 64, &offset) { in blorp_emit_sf_state()
114 blorp_emit_dynamic(batch, GENX(WM_STATE), wm, 64, &offset) { in blorp_emit_wm_state()
164 blorp_emit_dynamic(batch, GENX(COLOR_CALC_STATE), cc, 64, &offset) { in blorp_emit_color_calc_state()
180 blorp_emit(batch, GENX(3DSTATE_PIPELINED_POINTERS), pp) { in blorp_emit_pipeline()
191 blorp_emit(batch, GENX(CS_URB_STATE), curb); in blorp_emit_pipeline()
192 blorp_emit(batch, GENX(CONSTANT_BUFFER), curb); in blorp_emit_pipeline()
DgenX_blorp_exec.c279 blorp_emit(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) { in genX()