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Searched refs:GPR_64 (Results 1 – 14 of 14) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips64InstrInfo.td120 SLTI_FM<0xa>, GPR_64;
122 SLTI_FM<0xb>, GPR_64;
124 ADDI_FM<0xc>, GPR_64;
126 ADDI_FM<0xd>, GPR_64;
128 ADDI_FM<0xe>, GPR_64;
129 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64_relaxed>, LUI_FM, GPR_64;
145 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>, GPR_64;
146 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>, GPR_64;
148 GPR_64;
150 GPR_64;
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DMipsCondMov.td136 CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
143 CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
170 CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
177 CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
204 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
206 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
208 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
210 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
212 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
214 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
[all …]
DMips64r6InstrInfo.td153 def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
154 def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
165 def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6, GPR_64;
166 def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6, GPR_64;
168 def BEQC64 : BEQC_ENC, BEQC64_DESC, ISA_MIPS64R6, GPR_64;
169 def BEQZC64 : BEQZC_ENC, BEQZC64_DESC, ISA_MIPS64R6, GPR_64;
170 def BGEC64 : BGEC_ENC, BGEC64_DESC, ISA_MIPS64R6, GPR_64;
171 def BGEUC64 : BGEUC_ENC, BGEUC64_DESC, ISA_MIPS64R6, GPR_64;
172 def BGTZC64 : BGTZC_ENC, BGTZC64_DESC, ISA_MIPS64R6, GPR_64;
173 def BLEZC64 : BLEZC_ENC, BLEZC64_DESC, ISA_MIPS64R6, GPR_64;
[all …]
DMipsInstrFPU.td885 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, ISA_MIPS3, GPR_64, FGR_64;
886 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, ISA_MIPS3, GPR_64,
DMipsInstrInfo.td262 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
/external/llvm/lib/Target/Mips/
DMipsCondMov.td136 CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
143 CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
170 CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
177 CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
205 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
207 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
209 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
211 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
213 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
215 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
[all …]
DMips64r6InstrInfo.td125 def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
126 def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
DMips64InstrInfo.td636 GPR_64;
639 GPR_64;
DMipsInstrInfo.td230 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86GenRegisterBankInfo.def59 INSTR_3OP(BREAKDOWN(PMI_GPR64, 1)) // 9: GPR_64
DX86CallingConv.td32 list<Register> GPR_64 = [];
45 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle []
65 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
72 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
92 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>,
97 CCAssignToReg<RC.GPR_64>>>,
170 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>,
175 CCAssignToReg<RC.GPR_64>>>,
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelLowering.cpp1867 static const unsigned GPR_64[] = { // 64-bit registers. in LowerFormalArguments_Darwin() local
1885 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerFormalArguments_Darwin()
3127 static const unsigned GPR_64[] = { // 64-bit registers. in LowerCall_Darwin() local
3141 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerCall_Darwin()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp3569 static const MCPhysReg GPR_64[] = { // 64-bit registers. in LowerFormalArguments_Darwin() local
3584 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerFormalArguments_Darwin()
5736 static const MCPhysReg GPR_64[] = { // 64-bit registers. in LowerCall_Darwin() local
5748 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerCall_Darwin()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp4050 static const MCPhysReg GPR_64[] = { // 64-bit registers. in LowerFormalArguments_Darwin() local
4065 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerFormalArguments_Darwin()
6293 static const MCPhysReg GPR_64[] = { // 64-bit registers. in LowerCall_Darwin() local
6305 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerCall_Darwin()