| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/X86/ |
| D | subregister-index-operands.mir | 25 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG $edi, $al, %subreg.sub_8bit
29 %0 = INSERT_SUBREG $edi, $al, %subreg.sub_8bit
|
| D | unknown-subregister-index-op.mir | 23 %0 = INSERT_SUBREG $edi, $al, %subreg.bit8
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | detect-dead-lanes.mir | 57 # CHECK: %1 = INSERT_SUBREG %0, %sgpr1, {{[0-9]+}}
58 # CHECK: %2 = INSERT_SUBREG %0:sub2_sub3, %sgpr42, {{[0-9]+}}
67 # CHECK: %4 = INSERT_SUBREG %0, undef %3, {{[0-9]+}}
103 %1 = INSERT_SUBREG %0, %sgpr1, %subreg.sub3
104 %2 = INSERT_SUBREG %0:sub2_sub3, %sgpr42, %subreg.sub0
113 %4 = INSERT_SUBREG %0, %3, %subreg.sub0
151 # CHECK: %9 = INSERT_SUBREG undef %7, %8, {{[0-9]+}}
156 # CHECK: %12 = INSERT_SUBREG %10, undef %11, {{[0-9]+}}
201 %9 = INSERT_SUBREG %7, %8, %subreg.sub2_sub3
206 %12 = INSERT_SUBREG %10, %11, %subreg.sub0_sub1
|
| D | insert_subreg.ll | 4 ; Test that INSERT_SUBREG instructions don't have non-register operands after
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | detect-dead-lanes.mir | 46 # CHECK: %1:sreg_128 = INSERT_SUBREG %0, $sgpr1, %subreg.sub3
47 # CHECK: %2:sreg_64 = INSERT_SUBREG %0.sub2_sub3, $sgpr42, %subreg.sub0
56 # CHECK: %4:sreg_128 = INSERT_SUBREG %0, undef %3, %subreg.sub0
91 %1 = INSERT_SUBREG %0, $sgpr1, %subreg.sub3
92 %2 = INSERT_SUBREG %0.sub2_sub3, $sgpr42, %subreg.sub0
101 %4 = INSERT_SUBREG %0, %3, %subreg.sub0
139 # CHECK: %9:sreg_128 = INSERT_SUBREG undef %7, %8, %subreg.sub2_sub3
144 # CHECK: %12:sreg_128 = INSERT_SUBREG %10, undef %11, %subreg.sub0_sub1
188 %9 = INSERT_SUBREG %7, %8, %subreg.sub2_sub3
193 %12 = INSERT_SUBREG %10, %11, %subreg.sub0_sub1
|
| D | insert_subreg.ll | 4 ; Test that INSERT_SUBREG instructions don't have non-register operands after
|
| /external/llvm/test/CodeGen/MIR/X86/ |
| D | subregister-index-operands.mir | 15 # CHECK: %0 = INSERT_SUBREG %edi, %al, {{[0-9]+}}
27 %0 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit
|
| D | unknown-subregister-index-op.mir | 24 %0 = INSERT_SUBREG %edi, %al, %subreg.bit8
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | convert-rr-to-ri-instrs.mir | 1952 %8 = INSERT_SUBREG %9, killed %7, 1
2015 %8 = INSERT_SUBREG %9, killed %7, 1
2081 %4 = INSERT_SUBREG %5, killed %3, 1
2086 %9 = INSERT_SUBREG %10, killed %8, 1
2093 %14 = INSERT_SUBREG %15, killed %13, 1
2158 %4 = INSERT_SUBREG %5, killed %3, 1
2165 %9 = INSERT_SUBREG %10, killed %8, 1
2172 %14 = INSERT_SUBREG %15, killed %13, 1
2238 %4 = INSERT_SUBREG %5, killed %3, 1
2243 %9 = INSERT_SUBREG %10, killed %8, 1
[all …]
|
| /external/llvm/lib/CodeGen/ |
| D | DetectDeadLanes.cpp | 147 case TargetOpcode::INSERT_SUBREG: in lowersToCopies()
170 case TargetOpcode::INSERT_SUBREG: in isCrossCopy()
248 case TargetOpcode::INSERT_SUBREG: { in transferUsedLanes()
324 case TargetOpcode::INSERT_SUBREG: { in transferDefinedLanes()
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetOpcodes.h | 49 INSERT_SUBREG = 7, enumerator
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1369 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1375 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1533 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1537 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1541 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1545 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1549 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1553 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1560 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
2810 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1576 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1582 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1740 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1744 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1748 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1752 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1756 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1760 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1767 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3074 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | DetectDeadLanes.cpp | 145 case TargetOpcode::INSERT_SUBREG: in lowersToCopies()
168 case TargetOpcode::INSERT_SUBREG: in isCrossCopy()
246 case TargetOpcode::INSERT_SUBREG: { in transferUsedLanes()
322 case TargetOpcode::INSERT_SUBREG: { in transferDefinedLanes()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 758 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>,
804 (BBIT0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32),
808 (BBIT1 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32),
831 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
834 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
837 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
840 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
843 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
846 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
849 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
[all …]
|
| D | Mips64r6InstrInfo.td | 305 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
308 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
311 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
314 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
317 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenDAGISel.inc | 3377 /* 6670*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
3386 …st: (EXTRACT_SUBREG:{ *:[i32] } (SQRDMLAHv2i32_indexed:{ *:[v2i32] } (INSERT_SUBREG:{ *:[v2i32] } …
3451 /* 6836*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
3460 …st: (EXTRACT_SUBREG:{ *:[i32] } (SQRDMLAHv4i32_indexed:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } …
4037 /* 7915*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
4046 …st: (EXTRACT_SUBREG:{ *:[i32] } (SQRDMLSHv2i32_indexed:{ *:[v2i32] } (INSERT_SUBREG:{ *:[v2i32] } …
4111 /* 8081*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
4120 …st: (EXTRACT_SUBREG:{ *:[i32] } (SQRDMLSHv4i32_indexed:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } …
5411 /* 10462*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
5414 …// Dst: (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FCVTZSh:{ *:[f16] } FPR16:{ *:[f16…
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrAVX512.td | 1282 (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>;
1286 (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>;
1290 (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SrcRC:$src, Subreg)))>;
1455 (VINSERTF64x4Zrr (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1458 (VINSERTF64x4Zrr (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1461 (VINSERTI64x4Zrr (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1464 (VINSERTI64x4Zrr (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1467 (VINSERTI64x4Zrr (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1470 (VINSERTI64x4Zrr (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1557 (VINSERTF32x4Z256rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
[all …]
|
| D | X86InstrShiftRotate.td | 895 (INSERT_SUBREG
899 (INSERT_SUBREG
904 (INSERT_SUBREG
908 (INSERT_SUBREG
913 (INSERT_SUBREG
917 (INSERT_SUBREG
933 (INSERT_SUBREG
937 (INSERT_SUBREG
942 (INSERT_SUBREG
946 (INSERT_SUBREG
[all …]
|
| /external/llvm/include/llvm/Target/ |
| D | TargetOpcodes.def | 47 /// INSERT_SUBREG - This instruction takes three operands: a register that
53 HANDLE_TARGET_OPCODE(INSERT_SUBREG, 7)
58 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | i16lshr8pat.ll | 13 ; CHECK-NOT: INSERT_SUBREG
|
| D | crash-nosse.ll | 5 ; This test case produces INSERT_SUBREG 0, <undef> instructions that
|
| /external/llvm/test/CodeGen/X86/ |
| D | crash-nosse.ll | 5 ; This test case produces INSERT_SUBREG 0, <undef> instructions that
|
| D | i16lshr8pat.ll | 13 ; CHECK-NOT: INSERT_SUBREG
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | crash-nosse.ll | 5 ; This test case produces INSERT_SUBREG 0, <undef> instructions that
|