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Searched refs:IsThumb2 (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td833 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
843 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
857 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
1127 Requires<[IsThumb2]> {
1144 Requires<[HasT2ExtractPack, IsThumb2]> {
1160 Requires<[IsThumb2, HasT2ExtractPack]> {
1178 Requires<[HasT2ExtractPack, IsThumb2]> {
1191 Requires<[HasT2ExtractPack, IsThumb2]> {
1676 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1677 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
[all …]
DARMInstrFormats.td267 : InstAlias<Asm, Result, EmitPriority>, Requires<[IsThumb2]>;
368 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>;
406 list<Predicate> Predicates = [IsThumb2];
1198 list<Predicate> Predicates = [IsThumb2];
1219 list<Predicate> Predicates = [IsThumb2];
1232 list<Predicate> Predicates = [IsThumb2];
1316 : T2I <oops, iops, NoItinerary, opcstr, asm, pattern>, Requires<[IsThumb2]> {
1335 list<Predicate> Predicates = [IsThumb2];
1368 list<Predicate> Predicates = [IsThumb2];
1399 list<Predicate> Predicates = [IsThumb2, HasV6T2];
[all …]
DARMISelDAGToDAG.cpp3959 bool IsThumb2 = Subtarget->isThumb2(); in tryReadRegister() local
3973 Opcode = IsThumb2 ? ARM::t2MRC : ARM::MRC; in tryReadRegister()
3978 Opcode = IsThumb2 ? ARM::t2MRRC : ARM::MRRC; in tryReadRegister()
3997 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSbanked : ARM::MRSbanked, in tryReadRegister()
4057 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS, in tryReadRegister()
4066 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSsys_AR : ARM::MRSsys, DL, in tryReadRegister()
4080 bool IsThumb2 = Subtarget->isThumb2(); in tryWriteRegister() local
4093 Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR; in tryWriteRegister()
4098 Opcode = IsThumb2 ? ARM::t2MCRR : ARM::MCRR; in tryWriteRegister()
4118 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSRbanked : ARM::MSRbanked, in tryWriteRegister()
[all …]
DARMISelLowering.cpp7797 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) { in getLdOpcode() argument
7805 if (IsThumb2) in getLdOpcode()
7816 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) { in getStOpcode() argument
7824 if (IsThumb2) in getStOpcode()
7838 unsigned AddrOut, bool IsThumb1, bool IsThumb2) { in emitPostLd() argument
7839 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2); in emitPostLd()
7854 } else if (IsThumb2) { in emitPostLd()
7870 unsigned AddrOut, bool IsThumb1, bool IsThumb2) { in emitPostSt() argument
7871 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2); in emitPostSt()
7885 } else if (IsThumb2) { in emitPostSt()
[all …]
DARMInstrVFP.td1119 Requires<[IsThumb2, HasV6T2]>;
1125 Requires<[IsThumb2]>;
DARMInstrThumb.td308 let Predicates = [IsThumb2, HasV8];
DARMInstrInfo.td282 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb2.td706 Requires<[IsThumb2]> {
716 Requires<[IsThumb2]> {
730 Requires<[IsThumb2]> {
1018 Requires<[IsThumb2]> {
1035 Requires<[HasT2ExtractPack, IsThumb2]> {
1051 Requires<[IsThumb2, HasT2ExtractPack]> {
1069 Requires<[HasT2ExtractPack, IsThumb2]> {
1518 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1519 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1520 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
[all …]
DARMInstrFormats.td229 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>;
324 list<Predicate> Predicates = [IsThumb2];
1041 list<Predicate> Predicates = [IsThumb2];
1062 list<Predicate> Predicates = [IsThumb2];
1075 list<Predicate> Predicates = [IsThumb2];
1158 : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> {
1177 list<Predicate> Predicates = [IsThumb2];
1210 list<Predicate> Predicates = [IsThumb2];
1246 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1251 list<Predicate> Predicates = [IsThumb2];
DARMInstrThumb.td252 Requires<[IsThumb2]>;
DARMInstrInfo.td206 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td839 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
849 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
863 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
1155 Requires<[IsThumb2]>,
1164 Requires<[HasDSP, IsThumb2]>,
1173 Requires<[HasDSP, IsThumb2]>,
1682 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1683 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1684 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1705 def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
[all …]
DARMInstrFormats.td276 : InstAlias<Asm, Result, EmitPriority>, Requires<[IsThumb2]>;
279 Requires<[IsThumb2,UseNegativeImmediates]>;
380 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>;
426 list<Predicate> Predicates = [IsThumb2];
1023 list<Predicate> Predicates = [IsThumb2, HasDSP];
1026 list<Predicate> Predicates = [IsThumb2, UseMulOps, HasDSP];
1230 list<Predicate> Predicates = [IsThumb2];
1251 list<Predicate> Predicates = [IsThumb2];
1264 list<Predicate> Predicates = [IsThumb2];
1348 : T2I <oops, iops, NoItinerary, opcstr, asm, pattern>, Requires<[IsThumb2]> {
[all …]
DARMISelDAGToDAG.cpp3919 bool IsThumb2 = Subtarget->isThumb2(); in tryReadRegister() local
3933 Opcode = IsThumb2 ? ARM::t2MRC : ARM::MRC; in tryReadRegister()
3938 Opcode = IsThumb2 ? ARM::t2MRRC : ARM::MRRC; in tryReadRegister()
3957 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSbanked : ARM::MRSbanked, in tryReadRegister()
4011 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS, in tryReadRegister()
4020 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSsys_AR : ARM::MRSsys, DL, in tryReadRegister()
4034 bool IsThumb2 = Subtarget->isThumb2(); in tryWriteRegister() local
4047 Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR; in tryWriteRegister()
4052 Opcode = IsThumb2 ? ARM::t2MCRR : ARM::MCRR; in tryWriteRegister()
4072 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSRbanked : ARM::MSRbanked, in tryWriteRegister()
[all …]
DARMISelLowering.cpp8781 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) { in getLdOpcode() argument
8789 if (IsThumb2) in getLdOpcode()
8800 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) { in getStOpcode() argument
8808 if (IsThumb2) in getStOpcode()
8822 unsigned AddrOut, bool IsThumb1, bool IsThumb2) { in emitPostLd() argument
8823 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2); in emitPostLd()
8842 } else if (IsThumb2) { in emitPostLd()
8863 unsigned AddrOut, bool IsThumb1, bool IsThumb2) { in emitPostSt() argument
8864 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2); in emitPostSt()
8884 } else if (IsThumb2) { in emitPostSt()
[all …]
DARMInstrVFP.td1169 Requires<[IsThumb2, HasV6T2]>;
1175 Requires<[IsThumb2]>;
DARMInstrThumb.td325 let Predicates = [IsThumb2, HasV8];
DARMInstrInfo.td324 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,