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Searched refs:ItinData (Results 1 – 25 of 46) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/
DTargetInstrInfo.cpp49 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
51 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
55 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
65 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
68 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
73 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
77 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
80 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
88 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
90 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DScoreboardHazardRecognizer.cpp34 : ScheduleHazardRecognizer(), DebugType(ParentDebugType), ItinData(II), in ScoreboardHazardRecognizer()
41 if (ItinData && !ItinData->isEmpty()) { in ScoreboardHazardRecognizer()
43 if (ItinData->isEndMarker(idx)) in ScoreboardHazardRecognizer()
46 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer()
47 const InstrStage *E = ItinData->endStage(idx); in ScoreboardHazardRecognizer()
75 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer()
114 if (!ItinData || ItinData->isEmpty()) in getHazardType()
129 for (const InstrStage *IS = ItinData->beginStage(idx), in getHazardType()
130 *E = ItinData->endStage(idx); IS != E; ++IS) { in getHazardType()
174 if (!ItinData || ItinData->isEmpty()) in EmitInstruction()
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DTargetInstrInfo.cpp1040 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
1043 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
1051 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1053 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1056 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1058 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
1064 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
1071 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
1073 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
1077 int UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
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/external/llvm/lib/CodeGen/
DScoreboardHazardRecognizer.cpp31 : ScheduleHazardRecognizer(), DebugType(ParentDebugType), ItinData(II), in ScoreboardHazardRecognizer()
38 if (ItinData && !ItinData->isEmpty()) { in ScoreboardHazardRecognizer()
40 if (ItinData->isEndMarker(idx)) in ScoreboardHazardRecognizer()
43 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer()
44 const InstrStage *E = ItinData->endStage(idx); in ScoreboardHazardRecognizer()
72 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer()
111 if (!ItinData || ItinData->isEmpty()) in getHazardType()
126 for (const InstrStage *IS = ItinData->beginStage(idx), in getHazardType()
127 *E = ItinData->endStage(idx); IS != E; ++IS) { in getHazardType()
171 if (!ItinData || ItinData->isEmpty()) in EmitInstruction()
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DTargetInstrInfo.cpp981 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
984 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
992 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
994 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
997 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
999 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
1005 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
1012 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
1014 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
1018 int UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
DScoreboardHazardRecognizer.cpp35 ScheduleHazardRecognizer(), ItinData(II), DAG(SchedDAG), IssueWidth(0), in ScoreboardHazardRecognizer()
46 if (ItinData && !ItinData->isEmpty()) { in ScoreboardHazardRecognizer()
47 IssueWidth = ItinData->IssueWidth; in ScoreboardHazardRecognizer()
50 if (ItinData->isEndMarker(idx)) in ScoreboardHazardRecognizer()
53 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer()
54 const InstrStage *E = ItinData->endStage(idx); in ScoreboardHazardRecognizer()
109 if (!ItinData || ItinData->isEmpty()) in getHazardType()
124 for (const InstrStage *IS = ItinData->beginStage(idx), in getHazardType()
125 *E = ItinData->endStage(idx); IS != E; ++IS) { in getHazardType()
171 if (!ItinData || ItinData->isEmpty()) in EmitInstruction()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseInstrInfo.h204 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
208 int getOperandLatency(const InstrItineraryData *ItinData,
212 int getOperandLatency(const InstrItineraryData *ItinData,
222 int getVLDMDefCycle(const InstrItineraryData *ItinData,
226 int getLDMDefCycle(const InstrItineraryData *ItinData,
230 int getVSTMUseCycle(const InstrItineraryData *ItinData,
234 int getSTMUseCycle(const InstrItineraryData *ItinData,
238 int getOperandLatency(const InstrItineraryData *ItinData,
244 int getInstrLatency(const InstrItineraryData *ItinData,
247 int getInstrLatency(const InstrItineraryData *ItinData,
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DARMBaseInstrInfo.cpp1976 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
1978 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
1983 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
2082 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, in getVLDMDefCycle() argument
2089 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
2123 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, in getLDMDefCycle() argument
2130 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
2158 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, in getVSTMUseCycle() argument
2164 return ItinData->getOperandCycle(UseClass, UseIdx); in getVSTMUseCycle()
2198 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, in getSTMUseCycle() argument
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DARMHazardRecognizer.h37 ARMHazardRecognizer(const InstrItineraryData *ItinData, in ARMHazardRecognizer() argument
42 ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), TII(tii), in ARMHazardRecognizer()
/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.h278 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
281 int getOperandLatency(const InstrItineraryData *ItinData,
285 int getOperandLatency(const InstrItineraryData *ItinData,
306 int getVLDMDefCycle(const InstrItineraryData *ItinData,
310 int getLDMDefCycle(const InstrItineraryData *ItinData,
314 int getVSTMUseCycle(const InstrItineraryData *ItinData,
318 int getSTMUseCycle(const InstrItineraryData *ItinData,
322 int getOperandLatency(const InstrItineraryData *ItinData,
328 int getOperandLatencyImpl(const InstrItineraryData *ItinData,
337 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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DARMBaseInstrInfo.cpp2773 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, in getNumMicroOpsSwiftLdSt() argument
2778 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); in getNumMicroOpsSwiftLdSt()
3070 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
3072 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
3077 int ItinUOps = ItinData->getNumMicroOps(Class); in getNumMicroOps()
3080 return getNumMicroOpsSwiftLdSt(ItinData, MI); in getNumMicroOps()
3184 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, in getVLDMDefCycle() argument
3191 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3225 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, in getLDMDefCycle() argument
3232 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
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DARMHazardRecognizer.h35 ARMHazardRecognizer(const InstrItineraryData *ItinData, in ARMHazardRecognizer() argument
37 : ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), in ARMHazardRecognizer()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMBaseInstrInfo.h309 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
312 int getOperandLatency(const InstrItineraryData *ItinData,
316 int getOperandLatency(const InstrItineraryData *ItinData,
337 int getVLDMDefCycle(const InstrItineraryData *ItinData,
341 int getLDMDefCycle(const InstrItineraryData *ItinData,
345 int getVSTMUseCycle(const InstrItineraryData *ItinData,
349 int getSTMUseCycle(const InstrItineraryData *ItinData,
353 int getOperandLatency(const InstrItineraryData *ItinData,
359 int getOperandLatencyImpl(const InstrItineraryData *ItinData,
368 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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DARMHazardRecognizer.h35 ARMHazardRecognizer(const InstrItineraryData *ItinData, in ARMHazardRecognizer() argument
37 : ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), in ARMHazardRecognizer()
DARMBaseInstrInfo.cpp3103 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, in getNumMicroOpsSwiftLdSt() argument
3108 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); in getNumMicroOpsSwiftLdSt()
3400 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
3402 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
3407 int ItinUOps = ItinData->getNumMicroOps(Class); in getNumMicroOps()
3410 return getNumMicroOpsSwiftLdSt(ItinData, MI); in getNumMicroOps()
3514 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, in getVLDMDefCycle() argument
3521 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3571 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, in getLDMDefCycle() argument
3578 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
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/external/swiftshader/third_party/LLVM/utils/TableGen/
DSubtargetEmitter.cpp211 Record *ItinData, in FormItineraryStageString() argument
216 ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
255 void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData, in FormItineraryOperandCycleString() argument
259 ItinData->getValueAsListOfInts("OperandCycles"); in FormItineraryOperandCycleString()
273 Record *ItinData, in FormItineraryBypassString() argument
277 ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
375 Record *ItinData = ItinDataList[j]; in EmitStageAndOperandCycleData() local
380 FormItineraryStageString(Name, ItinData, ItinStageString, NStages); in EmitStageAndOperandCycleData()
385 FormItineraryOperandCycleString(ItinData, ItinOperandCycleString, in EmitStageAndOperandCycleData()
389 FormItineraryBypassString(Name, ItinData, ItinBypassString, in EmitStageAndOperandCycleData()
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DSubtargetEmitter.h39 Record *ItinData, std::string &ItinString,
41 void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
44 Record *ItinData,
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetInstrInfo.h627 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
643 virtual int getOperandLatency(const InstrItineraryData *ItinData,
647 virtual int getOperandLatency(const InstrItineraryData *ItinData,
654 virtual int getInstrLatency(const InstrItineraryData *ItinData,
658 virtual int getInstrLatency(const InstrItineraryData *ItinData,
671 bool hasHighOperandLatency(const InstrItineraryData *ItinData, in hasHighOperandLatency() argument
681 bool hasLowDefLatency(const InstrItineraryData *ItinData,
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp76 Record *ItinData, std::string &ItinString,
78 void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
81 Record *ItinData,
274 Record *ItinData, in FormItineraryStageString() argument
279 ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
318 void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData, in FormItineraryOperandCycleString() argument
322 ItinData->getValueAsListOfInts("OperandCycles"); in FormItineraryOperandCycleString()
336 Record *ItinData, in FormItineraryBypassString() argument
340 ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
439 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData() local
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/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h114 unsigned getInstrLatency(const InstrItineraryData *ItinData,
118 int getOperandLatency(const InstrItineraryData *ItinData,
122 int getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
125 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DSubtargetEmitter.cpp81 Record *ItinData, std::string &ItinString,
83 void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
86 Record *ItinData,
269 Record *ItinData, in FormItineraryStageString() argument
273 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
312 void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData, in FormItineraryOperandCycleString() argument
316 ItinData->getValueAsListOfInts("OperandCycles"); in FormItineraryOperandCycleString()
330 Record *ItinData, in FormItineraryBypassString() argument
333 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
431 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData() local
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/external/llvm/include/llvm/CodeGen/
DScoreboardHazardRecognizer.h91 const InstrItineraryData *ItinData; variable
105 ScoreboardHazardRecognizer(const InstrItineraryData *ItinData,
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DScoreboardHazardRecognizer.h94 const InstrItineraryData *ItinData; variable
108 ScoreboardHazardRecognizer(const InstrItineraryData *ItinData,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h169 unsigned getInstrLatency(const InstrItineraryData *ItinData,
173 int getOperandLatency(const InstrItineraryData *ItinData,
177 int getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
180 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
DPPCHazardRecognizers.h35 PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData, in PPCDispatchGroupSBHazardRecognizer() argument
37 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_), in PPCDispatchGroupSBHazardRecognizer()

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