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Searched refs:MDIO_DEVAD_NONE (Results 1 – 25 of 61) sorted by relevance

123

/external/u-boot/drivers/net/phy/
Dmarvell.c109 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extread()
112 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); in m88e1xxx_phy_extread()
113 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); in m88e1xxx_phy_extread()
114 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); in m88e1xxx_phy_extread()
122 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extwrite()
124 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); in m88e1xxx_phy_extwrite()
125 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); in m88e1xxx_phy_extwrite()
126 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); in m88e1xxx_phy_extwrite()
135 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
137 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in m88e1011s_config()
[all …]
Dvitesse.c73 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in vitesse_config()
76 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1, in vitesse_config()
89 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT); in vitesse_parse_status()
125 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in cis8204_config()
131 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
135 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
149 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL); in vsc8601_add_skew()
154 return phy_write(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL, ret); in vsc8601_add_skew()
174 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8574_config()
177 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19); in vsc8574_config()
[all …]
Dmeson-gxl.c43 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_startup()
46 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_startup()
49 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_startup()
52 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_startup()
57 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x8D80); in meson_gxl_startup()
62 wol = phy_read(phydev, MDIO_DEVAD_NONE, 0x15); in meson_gxl_startup()
66 lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); in meson_gxl_startup()
70 exp = phy_read(phydev, MDIO_DEVAD_NONE, MII_EXPANSION); in meson_gxl_startup()
103 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_phy_config()
104 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_phy_config()
[all …]
Dmscc.c142 phy_write(phydev, MDIO_DEVAD_NONE, in mscc_vsc8531_vsc8541_init_scripts()
147 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
149 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
154 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
155 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
160 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
163 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
168 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
169 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
174 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
[all …]
Datheros.c21 phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200); in ar8021_config()
22 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in ar8021_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); in ar8021_config()
33 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
35 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
41 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
43 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
59 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007); in ar8035_config()
60 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8035_config()
61 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8035_config()
[all …]
Dbroadcom.c42 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm_phy_write_misc()
45 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); in bcm_phy_write_misc()
47 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val); in bcm_phy_write_misc()
50 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val); in bcm_phy_write_misc()
52 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value); in bcm_phy_write_misc()
69 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS); in bcm54xx_parse_status()
129 return (phy_read(phydev, MDIO_DEVAD_NONE, reg) & 0x8FFF) | 0x8010; in bcm5482_read_wirespeed()
137 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in bcm5482_config()
139 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in bcm5482_config()
142 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm5482_config()
[all …]
Drealtek.c82 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211x_config()
87 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, in rtl8211x_config()
93 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in rtl8211x_config()
98 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg); in rtl8211x_config()
103 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, in rtl8211x_config()
105 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211x_config()
107 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG); in rtl8211x_config()
112 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg); in rtl8211x_config()
113 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, in rtl8211x_config()
117 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER); in rtl8211x_config()
[all …]
Dmicrel_ksz90x1.c51 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL); in ksz90xx_startup()
219 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9021_phy_extended_write()
221 return phy_write(phydev, MDIO_DEVAD_NONE, in ksz9021_phy_extended_write()
228 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum); in ksz9021_phy_extended_read()
229 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR); in ksz9021_phy_extended_read()
267 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000); in ksz9021_config()
292 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
295 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
298 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
301 return phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
[all …]
Dnatsemi.c21 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp83630_config()
22 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6); in dp83630_config()
23 ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE, in dp83630_config()
26 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG, in dp83630_config()
28 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0); in dp83630_config()
57 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp838xx_config()
67 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR); in dp83865_parse_status()
120 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in dp83848_parse_status()
Dphy.c48 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); in genphy_config_advert()
74 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE, adv); in genphy_config_advert()
81 bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_config_advert()
93 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in genphy_config_advert()
112 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, adv); in genphy_config_advert()
142 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_setup_forced()
155 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_restart_aneg()
165 ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_restart_aneg()
195 int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_config_aneg()
230 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
[all …]
Det1011c.c30 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
36 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); in et1011c_config()
46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG); in et1011c_parse_status()
57 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG); in et1011c_parse_status()
59 phy_write(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG, in et1011c_parse_status()
Dmicrel_ksz8xxx.c34 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO); in ksz_genconfig_bcastoff()
38 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO, in ksz_genconfig_bcastoff()
67 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO); in ksz8051_config()
69 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val); in ksz8051_config()
110 phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE, in ksz8895_write_smireg()
118 MDIO_DEVAD_NONE, smireg_to_reg(smireg));
Ddavicom.c28 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE); in dm9161_config()
30 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCR, in dm9161_config()
33 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_10BTCSR, in dm9161_config()
45 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR); in dm9161_parse_status()
Dti.c231 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); in dp83867_config()
232 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, in dp83867_config()
236 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, in dp83867_config()
242 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, in dp83867_config()
252 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2); in dp83867_config()
257 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, in dp83867_config()
263 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0); in dp83867_config()
Db53.c126 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_op()
133 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_op()
140 v = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_op()
162 *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_read8()
176 *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_read16()
190 *val = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_read32()
192 *val |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_read32()
210 temp |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_read48()
231 temp |= bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_read64()
244 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_write8()
[all …]
/external/u-boot/board/spear/x600/
Dx600.c76 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in board_phy_config()
77 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in board_phy_config()
83 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); in board_phy_config()
110 phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); in board_phy_config()
116 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); in board_phy_config()
119 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); in board_phy_config()
120 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); in board_phy_config()
123 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); in board_phy_config()
126 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); in board_phy_config()
129 phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); in board_phy_config()
/external/u-boot/drivers/net/pfe_eth/
Dpfe_mdio.c60 if (dev_addr == MDIO_DEVAD_NONE) { in pfe_phy_read()
71 if (dev_addr == MDIO_DEVAD_NONE) in pfe_phy_read()
115 if (dev_addr == MDIO_DEVAD_NONE) { in pfe_phy_write()
126 if (dev_addr == MDIO_DEVAD_NONE) in pfe_phy_write()
170 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0); in pfe_configure_serdes()
171 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1); in pfe_configure_serdes()
172 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x2); in pfe_configure_serdes()
173 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x3); in pfe_configure_serdes()
176 pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000); in pfe_configure_serdes()
185 pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value); in pfe_configure_serdes()
[all …]
/external/u-boot/board/compulab/cl-som-imx7/
Dcl-som-imx7.c135 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); in cl_som_imx7_rgmii_rework()
136 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); in cl_som_imx7_rgmii_rework()
137 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); in cl_som_imx7_rgmii_rework()
138 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in cl_som_imx7_rgmii_rework()
140 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in cl_som_imx7_rgmii_rework()
143 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in cl_som_imx7_rgmii_rework()
144 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in cl_som_imx7_rgmii_rework()
145 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in cl_som_imx7_rgmii_rework()
147 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in cl_som_imx7_rgmii_rework()
150 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in cl_som_imx7_rgmii_rework()
[all …]
/external/u-boot/board/Marvell/db-mv784mp-gp/
Ddb-mv784mp-gp.c95 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4); in board_phy_config()
97 phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140); in board_phy_config()
99 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0); in board_phy_config()
102 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4); in board_phy_config()
104 phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg); in board_phy_config()
107 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); in board_phy_config()
108 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); in board_phy_config()
111 reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG); in board_phy_config()
113 phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg); in board_phy_config()
/external/u-boot/board/congatec/cgtqmx6eval/
Dcgtqmx6eval.c282 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in board_eth_init()
283 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in board_eth_init()
331 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in mx6_rgmii_rework()
332 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in mx6_rgmii_rework()
336 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
337 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4); in mx6_rgmii_rework()
338 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); in mx6_rgmii_rework()
339 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000); in mx6_rgmii_rework()
341 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
342 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5); in mx6_rgmii_rework()
[all …]
/external/u-boot/board/gdsys/a38x/
Dihs_phys.c32 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0004); in ihs_phy_config()
33 reg = phy_read(phydev, MDIO_DEVAD_NONE, 16); in ihs_phy_config()
35 phy_write(phydev, MDIO_DEVAD_NONE, 16, reg); in ihs_phy_config()
41 reg = phy_read(phydev, MDIO_DEVAD_NONE, 26); in ihs_phy_config()
47 phy_write(phydev, MDIO_DEVAD_NONE, 26, reg); in ihs_phy_config()
50 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); in ihs_phy_config()
51 reg = phy_read(phydev, MDIO_DEVAD_NONE, 4); in ihs_phy_config()
53 phy_write(phydev, MDIO_DEVAD_NONE, 4, reg); in ihs_phy_config()
54 reg = phy_read(phydev, MDIO_DEVAD_NONE, 9); in ihs_phy_config()
56 phy_write(phydev, MDIO_DEVAD_NONE, 9, reg); in ihs_phy_config()
[all …]
/external/u-boot/board/k+p/kp_imx6q_tpc/
Dkp_imx6q_tpc.c140 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in ar8031_phy_fixup()
141 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8031_phy_fixup()
142 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8031_phy_fixup()
144 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in ar8031_phy_fixup()
147 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in ar8031_phy_fixup()
150 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in ar8031_phy_fixup()
151 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in ar8031_phy_fixup()
153 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in ar8031_phy_fixup()
/external/u-boot/board/technexion/pico-imx7d/
Dpico-imx7d.c192 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in board_phy_config()
193 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in board_phy_config()
194 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in board_phy_config()
196 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in board_phy_config()
199 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in board_phy_config()
202 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in board_phy_config()
203 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in board_phy_config()
205 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in board_phy_config()
/external/u-boot/board/compulab/cm_fx6/
Dcm_fx6.c372 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); in mx6_rgmii_rework()
373 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); in mx6_rgmii_rework()
374 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); in mx6_rgmii_rework()
375 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in mx6_rgmii_rework()
377 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in mx6_rgmii_rework()
380 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in mx6_rgmii_rework()
381 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in mx6_rgmii_rework()
382 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in mx6_rgmii_rework()
384 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in mx6_rgmii_rework()
387 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in mx6_rgmii_rework()
[all …]
/external/u-boot/board/tbs/tbs2910/
Dtbs2910.c366 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in ar8035_phy_fixup()
367 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8035_phy_fixup()
368 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8035_phy_fixup()
370 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in ar8035_phy_fixup()
373 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in ar8035_phy_fixup()
376 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in ar8035_phy_fixup()
377 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in ar8035_phy_fixup()
379 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in ar8035_phy_fixup()

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