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Searched refs:ODT (Results 1 – 25 of 39) sorted by relevance

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/external/u-boot/board/buffalo/lsxl/
Dkwbimage-lsxhl.cfg114 # bit2: 1, ODT control Rtt[0] (Rtt=1, 75 ohm termination)
116 # bit6: 0, ODT control Rtt[1] (Rtt=1, 75 ohm termination)
136 # DDR2 ODT Read Timing (default values)
141 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
145 # DDR2 ODT Write Timing (default values)
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
177 # DDR ODT Control (Low)
186 # DDR ODT Control (High)
[all …]
Dkwbimage-lschl.cfg114 # bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
116 # bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
136 # DDR2 ODT Read Timing (default values)
141 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
145 # DDR2 ODT Write Timing (default values)
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
177 # DDR ODT Control (Low)
186 # DDR ODT Control (High)
[all …]
/external/u-boot/board/d-link/dns325/
Dkwbimage.cfg105 # bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
107 # bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
126 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing
130 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
131 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
134 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing
137 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
138 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
160 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
168 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
[all …]
/external/u-boot/board/keymile/km_arm/
Dkwbimage-memphis.cfg110 # bit2: 1, DDR ODT control lsd disabled
112 # bit6: 0, DDR ODT control msb disabled
135 # bit15-12: 0100, internal ODT assertion 4 cycles after read
136 # bit19-16: 1000, internal ODT de-assertion 8 cycles after read
142 # bit11-8 : 0100, internal ODT assertion x cycles after write
143 # bit15-12: 1000, internal ODT de-assertion x cycles after write
157 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
161 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
162 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
166 DATA 0xFFD0149C 0x0000F801 # CPU ODT Control
[all …]
Dkwbimage_128M16_1.cfg173 # bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0]
175 # bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1]
198 # (ODT turn off delay 2,5 clk cycles)
199 # bit 15-12: 4, internal ODT time based on bit 7-4
201 # bit 19-16: 8, internal ODT de-assertion based on bit 11-8
208 # bit 11-8: 4, internal ODT assertion 2 cycles after write start command
210 # bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
228 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
238 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
239 # bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
[all …]
Dkwbimage_256M8_1.cfg173 # bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0]
175 # bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1]
198 # (ODT turn off delay 2,5 clk cycles)
199 # bit 15-12: 4, internal ODT time based on bit 7-4
201 # bit 19-16: 8, internal ODT de-assertion based on bit 11-8
208 # bit 11-8: 4, internal ODT assertion 2 cycles after write start command
210 # bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
228 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
238 DATA 0xFFD01498 0x00000004 # DDR ODT Control (High)
239 # bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
[all …]
Dkwbimage.cfg107 # bit2: 1, DDR ODT control lsd disabled
109 # bit6: 1, DDR ODT control msb, enabled
142 DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
146 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
147 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
151 DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control
152 # bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
153 # bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
155 # bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
/external/u-boot/board/Marvell/openrd/
Dkwbimage.cfg95 # bit2: 0, DDR ODT control lsd (disabled)
97 # bit6: 1, DDR ODT control msb, (disabled)
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
133 DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
138 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
140 DATA 0xFFD0149C 0x0000E40f # CPU ODT Control
141 # bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
142 # bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
143 # bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
[all …]
/external/u-boot/board/LaCie/netspace_v2/
Dkwbimage-is2.cfg95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
131 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
135 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
140 DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
[all …]
Dkwbimage.cfg95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
131 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
135 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
140 DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
[all …]
Dkwbimage-ns2l.cfg95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
131 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
135 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
140 DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
[all …]
/external/u-boot/board/LaCie/net2big_v2/
Dkwbimage.cfg95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
116 DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
131 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
135 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
140 DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
[all …]
/external/clang/lib/Serialization/
DMultiOnDiskHashTable.h117 auto *ODT = Table::getFromOpaqueValue(T).template get<OnDiskTable *>(); in removeOverriddenTables() local
118 bool Remove = Files.count(ODT->File); in removeOverriddenTables()
120 delete ODT; in removeOverriddenTables() local
136 for (auto *ODT : tables()) { in condense()
137 auto &HT = ODT->Table; in condense()
151 Merged->Files.push_back(ODT->File); in condense()
152 delete ODT; in condense() local
232 for (auto *ODT : tables()) { in find()
233 auto &HT = ODT->Table; in find()
257 for (auto *ODT : tables()) { in findAll()
[all …]
/external/u-boot/board/Marvell/guruplug/
Dkwbimage.cfg95 # bit2: 0, DDR ODT control lsd (disabled)
97 # bit6: 1, DDR ODT control msb, (disabled)
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
133 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
134 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
135 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
139 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
/external/u-boot/board/Seagate/goflexhome/
Dkwbimage.cfg101 # bit2: 0, DDR ODT control lsd (disabled)
103 # bit6: 1, DDR ODT control msb, (disabled)
122 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
123 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
139 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
140 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
141 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
145 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
/external/u-boot/board/Marvell/sheevaplug/
Dkwbimage.cfg95 # bit2: 0, DDR ODT control lsd (disabled)
97 # bit6: 1, DDR ODT control msb, (disabled)
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
133 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
134 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
135 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
139 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
/external/u-boot/board/Synology/ds109/
Dkwbimage.cfg99 # bit2: 0, DDR ODT control lsd (disabled)
101 # bit6: 1, DDR ODT control msb, (disabled)
120 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
121 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
139 DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low)
140 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
141 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
145 DATA 0xFFD0149C 0x0000F80F # CPU ODT Control
Dopenocd.cfg63 mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
64 mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
65 mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register
/external/u-boot/board/Seagate/dockstar/
Dkwbimage.cfg98 # bit2: 0, DDR ODT control lsd (disabled)
100 # bit6: 1, DDR ODT control msb, (disabled)
119 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
120 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
136 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
137 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
138 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
142 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
/external/u-boot/board/Marvell/dreamplug/
Dkwbimage.cfg96 # bit2: 0, DDR ODT control lsd (disabled)
98 # bit6: 1, DDR ODT control msb, (disabled)
117 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
118 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
134 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
135 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
140 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
/external/u-boot/board/iomega/iconnect/
Dkwbimage.cfg95 # bit2: 0, DDR ODT control lsd (disabled)
97 # bit6: 1, DDR ODT control msb, (disabled)
116 DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
133 DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
139 DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
140 # bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
144 DATA 0xffd0149c 0x0000e803 # CPU ODT Control
/external/u-boot/board/cloudengines/pogo_e02/
Dkwbimage.cfg99 # bit2: 0, DDR ODT control lsd (disabled)
101 # bit6: 1, DDR ODT control msb, (disabled)
120 DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
121 DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
137 DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
143 DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
144 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
148 DATA 0xffd0149c 0x0000e803 # CPU ODT Control
/external/u-boot/board/raidsonic/ib62x0/
Dkwbimage.cfg96 # bit2: 1, DDR ODT control lsd (disabled)
98 # bit6: 0, DDR ODT control msb, (disabled)
117 DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
118 DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
134 DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
140 DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
141 # bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
145 DATA 0xffd0149c 0x0000e803 # CPU ODT Control
/external/u-boot/board/Seagate/nas220/
Dkwbimage.cfg101 # bit2: 0, DDR ODT control lsd (disabled)
103 # bit6: 1, DDR ODT control msb, (disabled)
136 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
137 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
138 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
142 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
/external/u-boot/doc/device-tree-bindings/clock/
Drockchip,rk3288-dmc.txt21 …t-disable-freq: if ddr clock frequency low than odt-disable-freq,this driver should disable DDR ODT
110 odt - 1 to enable DDR ODT, 0 to disable

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