Home
last modified time | relevance | path

Searched refs:Op (Results 1 – 25 of 1920) sorted by relevance

12345678910>>...77

/external/swiftshader/third_party/llvm-7.0/llvm/lib/DebugInfo/DWARF/
DDWARFExpression.cpp27 typedef DWARFExpression::Operation Op; in getDescriptions() typedef
28 typedef Op::Description Desc; in getDescriptions()
31 Descriptions[DW_OP_addr] = Desc(Op::Dwarf2, Op::SizeAddr); in getDescriptions()
32 Descriptions[DW_OP_deref] = Desc(Op::Dwarf2); in getDescriptions()
33 Descriptions[DW_OP_const1u] = Desc(Op::Dwarf2, Op::Size1); in getDescriptions()
34 Descriptions[DW_OP_const1s] = Desc(Op::Dwarf2, Op::SignedSize1); in getDescriptions()
35 Descriptions[DW_OP_const2u] = Desc(Op::Dwarf2, Op::Size2); in getDescriptions()
36 Descriptions[DW_OP_const2s] = Desc(Op::Dwarf2, Op::SignedSize2); in getDescriptions()
37 Descriptions[DW_OP_const4u] = Desc(Op::Dwarf2, Op::Size4); in getDescriptions()
38 Descriptions[DW_OP_const4s] = Desc(Op::Dwarf2, Op::SignedSize4); in getDescriptions()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp54 SDValue LegalizeOp(SDValue Op);
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
60 SDValue UnrollVSETCC(SDValue Op);
66 SDValue Expand(SDValue Op);
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
76 SDValue ExpandSEXTINREG(SDValue Op);
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
99 SDValue ExpandBSWAP(SDValue Op);
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp75 SDValue LegalizeOp(SDValue Op);
78 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
81 SDValue UnrollVSETCC(SDValue Op);
87 SDValue Expand(SDValue Op);
94 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
97 SDValue ExpandSEXTINREG(SDValue Op);
104 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
111 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
117 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
120 SDValue ExpandBSWAP(SDValue Op);
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineOperand.h589 MachineOperand Op(MachineOperand::MO_Immediate); in CreateImm()
590 Op.setImm(Val); in CreateImm()
591 return Op; in CreateImm()
595 MachineOperand Op(MachineOperand::MO_CImmediate); in CreateCImm()
596 Op.Contents.CI = CI; in CreateCImm()
597 return Op; in CreateCImm()
601 MachineOperand Op(MachineOperand::MO_FPImmediate); in CreateFPImm()
602 Op.Contents.CFP = CFP; in CreateFPImm()
603 return Op; in CreateFPImm()
615 MachineOperand Op(MachineOperand::MO_Register);
[all …]
DMachineRegisterInfo.h834 MachineOperand *Op; variable
835 explicit defusechain_iterator(MachineOperand *op) : Op(op) { in defusechain_iterator()
848 assert(Op && "Cannot increment end iterator!"); in advance()
849 Op = getNextOperandForReg(Op); in advance()
853 if (Op) { in advance()
854 if (Op->isUse()) in advance()
855 Op = nullptr; in advance()
857 assert(!Op->isDebug() && "Can't have debug defs"); in advance()
861 while (Op && ((!ReturnDefs && Op->isDef()) || in advance()
862 (SkipDebug && Op->isDebug()))) in advance()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp54 SDValue LegalizeOp(SDValue Op);
56 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
58 SDValue UnrollVSETCC(SDValue Op);
63 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
66 SDValue ExpandVSELECT(SDValue Op);
67 SDValue ExpandFNEG(SDValue Op);
71 SDValue PromoteVectorOp(SDValue Op);
104 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) { in TranslateLegalizeResults() argument
106 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i) in TranslateLegalizeResults()
107 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); in TranslateLegalizeResults()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenGlobalISel.inc586 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 49*/ 1271,
597 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
598 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
604 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
605 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
606 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp403 SDValue MipsSETargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const { in lowerSELECT() argument
405 return MipsTargetLowering::LowerOperation(Op, DAG); in lowerSELECT()
407 EVT ResTy = Op->getValueType(0); in lowerSELECT()
408 SDLoc DL(Op); in lowerSELECT()
413 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
414 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), in lowerSELECT()
415 Op->getOperand(2)); in lowerSELECT()
446 SDValue MipsSETargetLowering::LowerOperation(SDValue Op, in LowerOperation() argument
448 switch(Op.getOpcode()) { in LowerOperation()
449 case ISD::LOAD: return lowerLOAD(Op, DAG); in LowerOperation()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DMachineOperand.h253 static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
739 MachineOperand Op(MachineOperand::MO_Immediate); in CreateImm()
740 Op.setImm(Val); in CreateImm()
741 return Op; in CreateImm()
745 MachineOperand Op(MachineOperand::MO_CImmediate); in CreateCImm()
746 Op.Contents.CI = CI; in CreateCImm()
747 return Op; in CreateCImm()
751 MachineOperand Op(MachineOperand::MO_FPImmediate); in CreateFPImm()
752 Op.Contents.CFP = CFP; in CreateFPImm()
753 return Op; in CreateFPImm()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenGlobalISel.inc855 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 11, /*)*//*default:*//*Label 59*/ 7369,
867 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
868 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/AArch64::GPR32spRegClassID,
872 GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32spRegClassID,
885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/AArch64::GPR32spRegClassID,
886 GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_addsub_shifted_imm32,
898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AArch64::GPR32RegClassID,
[all …]
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp360 SDValue MipsSETargetLowering::LowerOperation(SDValue Op, in LowerOperation() argument
362 switch(Op.getOpcode()) { in LowerOperation()
363 case ISD::LOAD: return lowerLOAD(Op, DAG); in LowerOperation()
364 case ISD::STORE: return lowerSTORE(Op, DAG); in LowerOperation()
365 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); in LowerOperation()
366 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); in LowerOperation()
367 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); in LowerOperation()
368 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); in LowerOperation()
369 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); in LowerOperation()
370 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); in LowerOperation()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc758 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 43*/ 6645,
770 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
771 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
777 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
778 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
779 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
780 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineOperand.h472 MachineOperand Op(MachineOperand::MO_Immediate); in CreateImm()
473 Op.setImm(Val); in CreateImm()
474 return Op; in CreateImm()
478 MachineOperand Op(MachineOperand::MO_CImmediate); in CreateCImm()
479 Op.Contents.CI = CI; in CreateCImm()
480 return Op; in CreateCImm()
484 MachineOperand Op(MachineOperand::MO_FPImmediate); in CreateFPImm()
485 Op.Contents.CFP = CFP; in CreateFPImm()
486 return Op; in CreateFPImm()
495 MachineOperand Op(MachineOperand::MO_Register);
[all …]
/external/llvm/lib/Target/X86/InstPrinter/
DX86IntelInstPrinter.cpp54 void X86IntelInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op, in printSSEAVXCC() argument
56 int64_t Imm = MI->getOperand(Op).getImm(); in printSSEAVXCC()
94 void X86IntelInstPrinter::printXOPCC(const MCInst *MI, unsigned Op, in printXOPCC() argument
96 int64_t Imm = MI->getOperand(Op).getImm(); in printXOPCC()
110 void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op, in printRoundingControl() argument
112 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; in printRoundingControl()
125 const MCOperand &Op = MI->getOperand(OpNo); in printPCRelImm() local
126 if (Op.isImm()) in printPCRelImm()
127 O << formatImm(Op.getImm()); in printPCRelImm()
129 assert(Op.isExpr() && "unknown pcrel immediate operand"); in printPCRelImm()
[all …]
DX86ATTInstPrinter.cpp72 void X86ATTInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op, in printSSEAVXCC() argument
74 int64_t Imm = MI->getOperand(Op).getImm(); in printSSEAVXCC()
112 void X86ATTInstPrinter::printXOPCC(const MCInst *MI, unsigned Op, in printXOPCC() argument
114 int64_t Imm = MI->getOperand(Op).getImm(); in printXOPCC()
128 void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op, in printRoundingControl() argument
130 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; in printRoundingControl()
144 const MCOperand &Op = MI->getOperand(OpNo); in printPCRelImm() local
145 if (Op.isImm()) in printPCRelImm()
146 O << formatImm(Op.getImm()); in printPCRelImm()
148 assert(Op.isExpr() && "unknown pcrel immediate operand"); in printPCRelImm()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/
DMCInstrDescView.cpp60 for (auto &Op : Operands) in Instruction() local
61 if (Op.IsExplicit && Op.TiedToIndex < 0) { in Instruction()
63 Op.VariableIndex = VariableIndex; in Instruction()
68 for (auto &Op : Operands) in Instruction() local
69 if (Op.TiedToIndex >= 0) in Instruction()
70 Op.VariableIndex = Operands[Op.TiedToIndex].VariableIndex; in Instruction()
72 for (auto &Op : Operands) in Instruction() local
73 if (Op.VariableIndex >= 0) in Instruction()
74 Variables[Op.VariableIndex].TiedOperands.push_back(Op.Index); in Instruction()
78 for (const auto &Op : Operands) { in Instruction() local
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc827 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 25, /*)*//*default:*//*Label 48*/ 1711,
846 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
847 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8,
848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID,
849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID,
852 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
864 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID,
904 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
905 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/InstPrinter/
DX86ATTInstPrinter.cpp59 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op, in printSSECC() argument
61 switch (MI->getOperand(Op).getImm()) { in printSSECC()
80 const MCOperand &Op = MI->getOperand(OpNo); in print_pcrel_imm() local
81 if (Op.isImm()) in print_pcrel_imm()
83 O << (int)Op.getImm(); in print_pcrel_imm()
85 assert(Op.isExpr() && "unknown pcrel immediate operand"); in print_pcrel_imm()
86 O << *Op.getExpr(); in print_pcrel_imm()
92 const MCOperand &Op = MI->getOperand(OpNo); in printOperand() local
93 if (Op.isReg()) { in printOperand()
94 O << '%' << getRegisterName(Op.getReg()); in printOperand()
[all …]
DX86IntelInstPrinter.cpp49 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op, in printSSECC() argument
51 switch (MI->getOperand(Op).getImm()) { in printSSECC()
68 const MCOperand &Op = MI->getOperand(OpNo); in print_pcrel_imm() local
69 if (Op.isImm()) in print_pcrel_imm()
70 O << Op.getImm(); in print_pcrel_imm()
72 assert(Op.isExpr() && "unknown pcrel immediate operand"); in print_pcrel_imm()
73 O << *Op.getExpr(); in print_pcrel_imm()
84 const MCOperand &Op = MI->getOperand(OpNo); in printOperand() local
85 if (Op.isReg()) { in printOperand()
86 PrintRegName(O, getRegisterName(Op.getReg())); in printOperand()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/InstPrinter/
DX86IntelInstPrinter.cpp60 const MCOperand &Op = MI->getOperand(OpNo); in printOperand() local
61 if (Op.isReg()) { in printOperand()
62 printRegName(O, Op.getReg()); in printOperand()
63 } else if (Op.isImm()) { in printOperand()
64 O << formatImm((int64_t)Op.getImm()); in printOperand()
66 assert(Op.isExpr() && "unknown operand kind in printOperand"); in printOperand()
68 Op.getExpr()->print(O, &MAI); in printOperand()
72 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op, in printMemReference() argument
74 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference()
75 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); in printMemReference()
[all …]
DX86ATTInstPrinter.cpp80 const MCOperand &Op = MI->getOperand(OpNo); in printOperand() local
81 if (Op.isReg()) { in printOperand()
82 printRegName(O, Op.getReg()); in printOperand()
83 } else if (Op.isImm()) { in printOperand()
85 int64_t Imm = Op.getImm(); in printOperand()
104 assert(Op.isExpr() && "unknown operand kind in printOperand"); in printOperand()
106 Op.getExpr()->print(O, &MAI); in printOperand()
111 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op, in printMemReference() argument
113 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference()
114 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference()
[all …]
/external/spirv-llvm/lib/SPIRV/libSPIRV/
DSPIRVOpCode.h51 SPIRVMap<Op, std::string>::init() { in init()
52 #define _SPIRV_OP(x, ...) add(Op##x, #x); in init()
56 SPIRV_DEF_NAMEMAP(Op, OpCodeNameMap) in SPIRV_DEF_NAMEMAP() argument
58 inline bool isAtomicOpCode(Op OpCode) { in SPIRV_DEF_NAMEMAP()
65 inline bool isBinaryOpCode(Op OpCode) { in isBinaryOpCode()
71 inline bool isShiftOpCode(Op OpCode) { in isShiftOpCode()
76 inline bool isLogicalOpCode(Op OpCode) { in isLogicalOpCode()
81 inline bool isBitwiseOpCode(Op OpCode) { in isBitwiseOpCode()
86 inline bool isBinaryShiftLogicalBitwiseOpCode(Op OpCode) { in isBinaryShiftLogicalBitwiseOpCode()
92 inline bool isCmpOpCode(Op OpCode) { in isCmpOpCode()
[all …]
/external/llvm/include/llvm/MC/
DMCInst.h112 MCOperand Op; in createReg() local
113 Op.Kind = kRegister; in createReg()
114 Op.RegVal = Reg; in createReg()
115 return Op; in createReg()
118 MCOperand Op; in createImm() local
119 Op.Kind = kImmediate; in createImm()
120 Op.ImmVal = Val; in createImm()
121 return Op; in createImm()
124 MCOperand Op; in createFPImm() local
125 Op.Kind = kFPImmediate; in createFPImm()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.h558 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
579 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
596 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
605 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
628 virtual void LowerAsmOperandForConstraint(SDValue Op,
717 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
788 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
793 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
794 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
795 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCInst.h117 MCOperand Op; in createReg() local
118 Op.Kind = kRegister; in createReg()
119 Op.RegVal = Reg; in createReg()
120 return Op; in createReg()
124 MCOperand Op; in createImm() local
125 Op.Kind = kImmediate; in createImm()
126 Op.ImmVal = Val; in createImm()
127 return Op; in createImm()
131 MCOperand Op; in createFPImm() local
132 Op.Kind = kFPImmediate; in createFPImm()
[all …]

12345678910>>...77