| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIMachineScheduler.h | 405 std::set<unsigned> &OutRegs);
482 std::set<unsigned> OutRegs; in getOutRegs() local
484 OutRegs.insert(RegMaskPair.RegUnit); in getOutRegs()
486 return OutRegs; in getOutRegs()
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| D | SIMachineScheduler.cpp | 1522 const std::set<unsigned> &OutRegs = Block->getOutRegs(); in SIScheduleBlockScheduler() local
1524 if (OutRegs.find(Reg) == OutRegs.end()) in SIScheduleBlockScheduler()
1750 std::set<unsigned> &OutRegs) { in checkRegUsageImpact() argument
1766 for (unsigned Reg : OutRegs) { in checkRegUsageImpact()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 87 SmallVector<unsigned, 16> OutRegs; member
186 OutRegs.clear(); in clearOuts()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 97 SmallVector<unsigned, 16> OutRegs; member
193 OutRegs.clear(); in clearOuts()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIMachineScheduler.h | 396 std::set<unsigned> &OutRegs);
|
| D | SIMachineScheduler.cpp | 1597 std::set<unsigned> &OutRegs) { in checkRegUsageImpact() argument
1613 for (unsigned Reg : OutRegs) { in checkRegUsageImpact()
|
| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 3009 auto &OutRegs = CLI.OutRegs; in fastLowerCall() local
3215 OutRegs.push_back(VA.getLocReg()); in fastLowerCall()
3332 for (auto Reg : OutRegs) in fastLowerCall()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1176 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
1326 for (auto Reg : CLI.OutRegs) in fastLowerCall()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 3197 auto &OutRegs = CLI.OutRegs; in fastLowerCall() local
3423 OutRegs.push_back(VA.getLocReg()); in fastLowerCall()
3547 for (auto Reg : OutRegs) in fastLowerCall()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 794 unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size(); in selectPatchpoint()
812 for (auto Reg : CLI.OutRegs) in selectPatchpoint()
|
| D | SelectionDAGBuilder.cpp | 7075 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; in visitInlineAsm() local
7077 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), in visitInlineAsm()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1214 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
1545 for (auto Reg : CLI.OutRegs) in fastLowerCall()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 970 unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size(); in selectPatchpoint()
988 for (auto Reg : CLI.OutRegs) in selectPatchpoint()
|
| D | SelectionDAGBuilder.cpp | 7833 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; in visitInlineAsm() local
7835 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), in visitInlineAsm()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3072 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
3253 for (auto Reg : CLI.OutRegs) in fastLowerCall()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 2986 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
3167 for (auto Reg : CLI.OutRegs) in fastLowerCall()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 6263 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; in visitInlineAsm() local
6265 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), in visitInlineAsm()
|