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Searched refs:ProcResource (Results 1 – 25 of 53) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/
DResourcePressureView.cpp28 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in initialize() local
29 unsigned NumUnits = ProcResource.NumUnits; in initialize()
31 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in initialize()
35 R2VIndex += ProcResource.NumUnits; in initialize()
64 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printColumnNames() local
65 unsigned NumUnits = ProcResource.NumUnits; in printColumnNames()
67 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in printColumnNames()
104 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printResourcePressurePerIteration() local
105 unsigned NumUnits = ProcResource.NumUnits; in printResourcePressurePerIteration()
107 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in printResourcePressurePerIteration()
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DInstructionTables.cpp37 const MCProcResourceDesc &ProcResource = *SM.getProcResource(Index); in execute() local
38 unsigned NumUnits = ProcResource.NumUnits; in execute()
39 if (!ProcResource.SubUnitsIdxBegin) { in execute()
53 unsigned SubUnitIdx = ProcResource.SubUnitsIdxBegin[I1]; in execute()
DSchedulerStatistics.cpp80 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printSchedulerUsage() local
81 if (ProcResource.BufferSize <= 0) in printSchedulerUsage()
87 TempStream << ProcResource.Name << ", " << MaxUsedSlots << '/' in printSchedulerUsage()
88 << ProcResource.BufferSize << '\n'; in printSchedulerUsage()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkor.td38 def FalkorUnitB : ProcResource<1>; // Branch
39 def FalkorUnitLD : ProcResource<1>; // Load pipe
40 def FalkorUnitSD : ProcResource<1>; // Store data
41 def FalkorUnitST : ProcResource<1>; // Store pipe
42 def FalkorUnitX : ProcResource<1>; // Complex arithmetic
43 def FalkorUnitY : ProcResource<1>; // Simple arithmetic
44 def FalkorUnitZ : ProcResource<1>; // Simple arithmetic
46 def FalkorUnitVSD : ProcResource<1>; // Vector store data
47 def FalkorUnitVX : ProcResource<1>; // Vector X-pipe
48 def FalkorUnitVY : ProcResource<1>; // Vector Y-pipe
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DAArch64SchedExynosM3.td40 def M3UnitA : ProcResource<2>; // Simple integer
41 def M3UnitC : ProcResource<2>; // Simple and complex integer
42 def M3UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
43 def M3UnitB : ProcResource<2>; // Branch
44 def M3UnitL : ProcResource<2>; // Load
45 def M3UnitS : ProcResource<1>; // Store
46 def M3PipeF0 : ProcResource<1>; // FP #0
48 def M3UnitFMAC0 : ProcResource<1>; // FP multiplication
49 def M3UnitFADD0 : ProcResource<1>; // Simple FP
50 def M3UnitFCVT0 : ProcResource<1>; // FP conversion
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DAArch64SchedKryo.td41 def KryoUnitXA : ProcResource<1>; // Type X(A) micro-ops
42 def KryoUnitXB : ProcResource<1>; // Type X(B) micro-ops
43 def KryoUnitYA : ProcResource<1>; // Type Y(A) micro-ops
44 def KryoUnitYB : ProcResource<1>; // Type Y(B) micro-ops
53 def KryoUnitLSA : ProcResource<1>; // Type LS(A) micro-ops
54 def KryoUnitLSB : ProcResource<1>; // Type LS(B) micro-ops
DAArch64SchedExynosM1.td37 def M1UnitA : ProcResource<2>; // Simple integer
38 def M1UnitC : ProcResource<1>; // Simple and complex integer
39 def M1UnitD : ProcResource<1>; // Integer division (inside C, serialized)
40 def M1UnitB : ProcResource<2>; // Branch
41 def M1UnitL : ProcResource<1>; // Load
42 def M1UnitS : ProcResource<1>; // Store
43 def M1PipeF0 : ProcResource<1>; // FP #0
45 def M1UnitFMAC : ProcResource<1>; // FP multiplication
46 def M1UnitNAL0 : ProcResource<1>; // Simple vector
47 def M1UnitNMISC : ProcResource<1>; // Miscellanea
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DAArch64SchedA53.td37 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
40 def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
41 def A53UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
42 def A53UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division
43 def A53UnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store
44 def A53UnitB : ProcResource<1> { let BufferSize = 0; } // Branch
45 def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
46 def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
DAArch64SchedThunderX.td36 def THXT8XUnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
37 def THXT8XUnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
38 def THXT8XUnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division
39 def THXT8XUnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store
40 def THXT8XUnitBr : ProcResource<1> { let BufferSize = 0; } // Branch
41 def THXT8XUnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
42 def THXT8XUnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mul/Div/Sqrt
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCScheduleP9.td49 def DISPATCHER : ProcResource<12>;
58 def IP_AGEN : ProcResource<4>;
59 def IP_EXEC : ProcResource<4>;
60 def IP_EXECE : ProcResource<2> {
64 def IP_EXECO : ProcResource<2> {
71 def ALU : ProcResource<4>;
72 def ALUE : ProcResource<2> {
76 def ALUO : ProcResource<2> {
82 def DIV : ProcResource<2>;
85 def DP : ProcResource<4>;
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/external/llvm/lib/Target/X86/
DX86ScheduleBtVer2.td34 def JALU0 : ProcResource<1>; // Integer Pipe0: integer ALU0 (also handle FP->INT jam)
35 def JALU1 : ProcResource<1>; // Integer Pipe1: integer ALU1/MUL/DIV
36 def JLAGU : ProcResource<1>; // Integer Pipe2: LAGU
37 def JSAGU : ProcResource<1>; // Integer Pipe3: SAGU (also handles 3-operand LEA)
38 def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA
39 def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM
59 def JDiv : ProcResource<1>; // integer division
60 def JMul : ProcResource<1>; // integer multiplication
61 def JVALU0 : ProcResource<1>; // vector integer
62 def JVALU1 : ProcResource<1>; // vector integer
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DX86ScheduleSLM.td36 def IEC_RSV0 : ProcResource<1>;
37 def IEC_RSV1 : ProcResource<1>;
38 def FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
39 def FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }
40 def MEC_RSV : ProcResource<1>;
46 def SMDivider : ProcResource<1>;
47 def SMFPMultiplier : ProcResource<1>;
48 def SMFPDivider : ProcResource<1>;
DX86SchedSandyBridge.td37 def SBPort0 : ProcResource<1>;
38 def SBPort1 : ProcResource<1>;
39 def SBPort5 : ProcResource<1>;
43 def SBPort23 : ProcResource<2>;
48 def SBPort4 : ProcResource<1>;
61 def SBDivider : ProcResource<1>;
/external/llvm/lib/Target/AMDGPU/
DSISchedule.td58 def HWBranch : ProcResource<1> {
61 def HWExport : ProcResource<1> {
64 def HWLGKM : ProcResource<1> {
67 def HWSALU : ProcResource<1> {
70 def HWVMEM : ProcResource<1> {
73 def HWVALU : ProcResource<1> {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSISchedule.td67 def HWBranch : ProcResource<1> {
70 def HWExport : ProcResource<1> {
73 def HWLGKM : ProcResource<1> {
76 def HWSALU : ProcResource<1> {
79 def HWVMEM : ProcResource<1> {
82 def HWVALU : ProcResource<1> {
/external/llvm/lib/Target/AArch64/
DAArch64SchedM1.td33 def M1UnitA : ProcResource<2>; // Simple integer
34 def M1UnitC : ProcResource<1>; // Simple and complex integer
35 def M1UnitB : ProcResource<2>; // Branch
36 def M1UnitL : ProcResource<1>; // Load
37 def M1UnitS : ProcResource<1>; // Store
38 def M1PipeF0 : ProcResource<1>; // FP #0
39 def M1PipeF1 : ProcResource<1>; // FP #1
42 def M1UnitFMAC : ProcResource<1>; // FP multiplication
43 def M1UnitFCVT : ProcResource<1>; // FP conversion
44 def M1UnitNAL0 : ProcResource<1>; // Simple vector.
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DAArch64SchedKryo.td36 def KryoUnitXA : ProcResource<1>; // Type X(A) micro-ops
37 def KryoUnitXB : ProcResource<1>; // Type X(B) micro-ops
38 def KryoUnitYA : ProcResource<1>; // Type Y(A) micro-ops
39 def KryoUnitYB : ProcResource<1>; // Type Y(B) micro-ops
48 def KryoUnitLSA : ProcResource<1>; // Type LS(A) micro-ops
49 def KryoUnitLSB : ProcResource<1>; // Type LS(B) micro-ops
DAArch64SchedA53.td35 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
38 def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
39 def A53UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
40 def A53UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division
41 def A53UnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store
42 def A53UnitB : ProcResource<1> { let BufferSize = 0; } // Branch
43 def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
44 def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
/external/llvm/lib/Target/Mips/
DMipsScheduleP5600.td24 def P5600ALQ : ProcResource<1> { let BufferSize = 16; }
25 def P5600IssueALU : ProcResource<1> { let Super = P5600ALQ; }
39 def P5600AGQ : ProcResource<3> { let BufferSize = 16; }
40 def P5600IssueAL2 : ProcResource<1> { let Super = P5600AGQ; }
41 def P5600IssueCTISTD : ProcResource<1> { let Super = P5600AGQ; }
42 def P5600IssueLDST : ProcResource<1> { let Super = P5600AGQ; }
44 def P5600AL2Div : ProcResource<1>;
46 def P5600CTISTD : ProcResource<1>;
186 def P5600FPQ : ProcResource<3> { let BufferSize = 16; }
187 def P5600IssueFPUS : ProcResource<1> { let Super = P5600FPQ; }
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ScheduleBtVer2.td34 def JALU0 : ProcResource<1>; // Integer Pipe0: integer ALU0 (also handle FP->INT jam)
35 def JALU1 : ProcResource<1>; // Integer Pipe1: integer ALU1/MUL/DIV
36 def JLAGU : ProcResource<1>; // Integer Pipe2: LAGU
37 def JSAGU : ProcResource<1>; // Integer Pipe3: SAGU (also handles 3-operand LEA)
38 def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA
39 def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM
79 def JDiv : ProcResource<1>; // integer division
80 def JMul : ProcResource<1>; // integer multiplication
81 def JVALU0 : ProcResource<1>; // vector integer
82 def JVALU1 : ProcResource<1>; // vector integer
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DX86ScheduleSLM.td35 def SLM_IEC_RSV0 : ProcResource<1>;
36 def SLM_IEC_RSV1 : ProcResource<1>;
37 def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
38 def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }
39 def SLM_MEC_RSV : ProcResource<1>;
45 def SLMDivider : ProcResource<1>;
46 def SLMFPMultiplier : ProcResource<1>;
47 def SLMFPDivider : ProcResource<1>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsScheduleP5600.td30 def P5600ALQ : ProcResource<1> { let BufferSize = 16; }
31 def P5600IssueALU : ProcResource<1> { let Super = P5600ALQ; }
45 def P5600AGQ : ProcResource<3> { let BufferSize = 16; }
46 def P5600IssueAL2 : ProcResource<1> { let Super = P5600AGQ; }
47 def P5600IssueCTISTD : ProcResource<1> { let Super = P5600AGQ; }
48 def P5600IssueLDST : ProcResource<1> { let Super = P5600AGQ; }
50 def P5600AL2Div : ProcResource<1>;
52 def P5600CTISTD : ProcResource<1>;
218 def P5600FPQ : ProcResource<3> { let BufferSize = 16; }
219 def P5600IssueFPUS : ProcResource<1> { let Super = P5600FPQ; }
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DMipsScheduleGeneric.td40 def GenericALU : ProcResource<1> { let BufferSize = 1; }
41 def GenericIssueALU : ProcResource<1> { let Super = GenericALU; }
59 def GenericMDU : ProcResource<1> { let BufferSize = 1; }
60 def GenericIssueMDU : ProcResource<1> { let Super = GenericALU; }
61 def GenericIssueDIV : ProcResource<1> { let Super = GenericMDU; }
146 def GenericIssueCTISTD : ProcResource<1> { let Super = GenericALU; }
148 def GenericLDST : ProcResource<1> { let BufferSize = 1; }
149 def GenericIssueLDST : ProcResource<1> { let Super = GenericLDST; }
187 def GenericCOP0 : ProcResource<1> { let BufferSize = 1; }
189 def GenericIssueCOP0 : ProcResource<1> { let Super = GenericCOP0; }
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/external/llvm/lib/Target/Lanai/
DLanaiSchedule.td55 def ALU : ProcResource<1> { let BufferSize = 0; }
56 def LdSt : ProcResource<1> { let BufferSize = 0; }
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiSchedule.td55 def ALU : ProcResource<1> { let BufferSize = 0; }
56 def LdSt : ProcResource<1> { let BufferSize = 0; }

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