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Searched refs:ReadAdvance (Results 1 – 25 of 47) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkor.td104 // These ReadAdvance entries are not used in the Falkor sched model.
105 def : ReadAdvance<ReadI, 0>;
106 def : ReadAdvance<ReadISReg, 0>;
107 def : ReadAdvance<ReadIEReg, 0>;
108 def : ReadAdvance<ReadIM, 0>;
109 def : ReadAdvance<ReadIMA, 0>;
110 def : ReadAdvance<ReadID, 0>;
111 def : ReadAdvance<ReadExtrHi, 0>;
112 def : ReadAdvance<ReadAdrBase, 0>;
113 def : ReadAdvance<ReadVLD, 0>;
DAArch64SchedKryo.td111 def : ReadAdvance<ReadI, 0>;
112 def : ReadAdvance<ReadISReg, 0>;
113 def : ReadAdvance<ReadIEReg, 0>;
114 def : ReadAdvance<ReadIM, 0>;
115 def : ReadAdvance<ReadIMA, 0>;
116 def : ReadAdvance<ReadID, 0>;
117 def : ReadAdvance<ReadExtrHi, 0>;
118 def : ReadAdvance<ReadAdrBase, 0>;
119 def : ReadAdvance<ReadVLD, 0>;
DAArch64SchedThunderX.td192 def : ReadAdvance<ReadExtrHi, 1>;
193 def : ReadAdvance<ReadAdrBase, 2>;
194 def : ReadAdvance<ReadVLD, 2>;
200 // ReadAdvance applies to Extended registers as well, even though there is
202 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
226 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
230 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
236 def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
DAArch64SchedA53.td149 def : ReadAdvance<ReadExtrHi, 0>;
150 def : ReadAdvance<ReadAdrBase, 0>;
151 def : ReadAdvance<ReadVLD, 0>;
156 // ReadAdvance applies to Extended registers as well, even though there is
158 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
182 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
186 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
192 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
DAArch64SchedExynosM1.td231 def : ReadAdvance<ReadI, 0>;
232 def : ReadAdvance<ReadISReg, 0>;
233 def : ReadAdvance<ReadIEReg, 0>;
234 def : ReadAdvance<ReadIM, 0>;
236 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
237 def : ReadAdvance<ReadID, 0>;
238 def : ReadAdvance<ReadExtrHi, 0>;
239 def : ReadAdvance<ReadAdrBase, 0>;
240 def : ReadAdvance<ReadVLD, 0>;
DAArch64SchedExynosM3.td275 def : ReadAdvance<ReadI, 0>;
276 def : ReadAdvance<ReadISReg, 0>;
277 def : ReadAdvance<ReadIEReg, 0>;
278 def : ReadAdvance<ReadIM, 0>;
280 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
281 def : ReadAdvance<ReadID, 0>;
282 def : ReadAdvance<ReadExtrHi, 0>;
283 def : ReadAdvance<ReadAdrBase, 0>;
284 def : ReadAdvance<ReadVLD, 0>;
DAArch64SchedA57.td111 def : ReadAdvance<ReadI, 0>;
112 def : ReadAdvance<ReadISReg, 0>;
113 def : ReadAdvance<ReadIEReg, 0>;
114 def : ReadAdvance<ReadIM, 0>;
115 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
116 def : ReadAdvance<ReadID, 0>;
117 def : ReadAdvance<ReadExtrHi, 0>;
118 def : ReadAdvance<ReadAdrBase, 0>;
119 def : ReadAdvance<ReadVLD, 0>;
DAArch64SchedCyclone.td185 def : ReadAdvance<ReadExtrHi, 1>;
634 def : ReadAdvance<ReadVLD, 5>;
864 def : ReadAdvance<ReadI, 0>;
865 def : ReadAdvance<ReadISReg, 0>;
866 def : ReadAdvance<ReadIEReg, 0>;
867 def : ReadAdvance<ReadIM, 0>;
868 def : ReadAdvance<ReadIMA, 0>;
869 def : ReadAdvance<ReadID, 0>;
DAArch64SchedThunderX2T99.td356 def : ReadAdvance<ReadI, 0>;
357 def : ReadAdvance<ReadISReg, 0>;
358 def : ReadAdvance<ReadIEReg, 0>;
359 def : ReadAdvance<ReadIM, 0>;
360 def : ReadAdvance<ReadIMA, 0>;
361 def : ReadAdvance<ReadID, 0>;
362 def : ReadAdvance<ReadExtrHi, 0>;
363 def : ReadAdvance<ReadAdrBase, 0>;
364 def : ReadAdvance<ReadVLD, 0>;
/external/llvm/lib/Target/AArch64/
DAArch64SchedKryo.td106 def : ReadAdvance<ReadI, 0>;
107 def : ReadAdvance<ReadISReg, 0>;
108 def : ReadAdvance<ReadIEReg, 0>;
109 def : ReadAdvance<ReadIM, 0>;
110 def : ReadAdvance<ReadIMA, 0>;
111 def : ReadAdvance<ReadID, 0>;
112 def : ReadAdvance<ReadExtrHi, 0>;
113 def : ReadAdvance<ReadAdrBase, 0>;
114 def : ReadAdvance<ReadVLD, 0>;
DAArch64SchedM1.td154 def : ReadAdvance<ReadI, 0>;
155 def : ReadAdvance<ReadISReg, 0>;
156 def : ReadAdvance<ReadIEReg, 0>;
157 def : ReadAdvance<ReadIM, 0>;
160 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
161 def : ReadAdvance<ReadID, 0>;
162 def : ReadAdvance<ReadExtrHi, 0>;
163 def : ReadAdvance<ReadAdrBase, 0>;
164 def : ReadAdvance<ReadVLD, 0>;
DAArch64SchedA53.td147 def : ReadAdvance<ReadExtrHi, 0>;
148 def : ReadAdvance<ReadAdrBase, 0>;
149 def : ReadAdvance<ReadVLD, 0>;
154 // ReadAdvance applies to Extended registers as well, even though there is
156 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
180 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
184 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
190 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
DAArch64SchedVulcan.td192 def : ReadAdvance<ReadI, 0>;
193 def : ReadAdvance<ReadISReg, 0>;
194 def : ReadAdvance<ReadIEReg, 0>;
195 def : ReadAdvance<ReadIM, 0>;
196 def : ReadAdvance<ReadIMA, 0>;
197 def : ReadAdvance<ReadID, 0>;
198 def : ReadAdvance<ReadExtrHi, 0>;
199 def : ReadAdvance<ReadAdrBase, 0>;
200 def : ReadAdvance<ReadVLD, 0>;
DAArch64SchedA57.td109 def : ReadAdvance<ReadI, 0>;
110 def : ReadAdvance<ReadISReg, 0>;
111 def : ReadAdvance<ReadIEReg, 0>;
112 def : ReadAdvance<ReadIM, 0>;
113 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
114 def : ReadAdvance<ReadID, 0>;
115 def : ReadAdvance<ReadExtrHi, 0>;
116 def : ReadAdvance<ReadAdrBase, 0>;
117 def : ReadAdvance<ReadVLD, 0>;
DAArch64SchedCyclone.td183 def : ReadAdvance<ReadExtrHi, 1>;
632 def : ReadAdvance<ReadVLD, 5>;
862 def : ReadAdvance<ReadI, 0>;
863 def : ReadAdvance<ReadISReg, 0>;
864 def : ReadAdvance<ReadIEReg, 0>;
865 def : ReadAdvance<ReadIM, 0>;
866 def : ReadAdvance<ReadIMA, 0>;
867 def : ReadAdvance<ReadID, 0>;
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/
DInstruction.cpp55 void WriteState::addUser(ReadState *User, int ReadAdvance) { in addUser() argument
60 unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance); in addUser()
65 std::pair<ReadState *, int> NewPair(User, ReadAdvance); in addUser()
DDispatchStage.cpp85 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in updateRAWDependencies() local
86 WS.addUser(&RS, ReadAdvance); in updateRAWDependencies()
DInstruction.h131 void addUser(ReadState *Use, int ReadAdvance);
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMScheduleR52.td88 def : ReadAdvance<ReadALU, 1>; // Operand needed in EX1 stage
89 def : ReadAdvance<ReadALUsr, 0>; // Shift operands needed in ISS
90 def : ReadAdvance<ReadMUL, 0>;
91 def : ReadAdvance<ReadMAC, 0>;
128 def : ReadAdvance<ReadFPMUL, 1>; // mul operand read in F1
129 def : ReadAdvance<ReadFPMAC, 1>; // fp-mac operand read in F1
135 def : ReadAdvance<R52Read_ISS, 0>;
136 def : ReadAdvance<R52Read_EX1, 1>;
137 def : ReadAdvance<R52Read_EX2, 2>;
138 def : ReadAdvance<R52Read_F0, 0>;
[all …]
DARMScheduleA57.td275 def : ReadAdvance<ReadMUL, 0>;
764 def : ReadAdvance<ReadFPMUL, 0>;
777 // def : ReadAdvance<A57ReadVFMA, 5, [A57WriteVFMA]>;
778 // def : ReadAdvance<A57ReadVFMA, 4, [A57WriteVMUL]>;
1039 // (4 or 3 ReadAdvance)
1052 // (4 or 3 ReadAdvance)
1065 // (4 or 3 ReadAdvance)
1078 // (3 or 2 ReadAdvance)
1103 // 4cyc F1, 1cyc for accumulate sequence (3cyc ReadAdvance)
1109 // 4cyc F1, 1cyc for accumulate sequence (3cyc ReadAdvance)
[all …]
/external/llvm/include/llvm/Target/
DTargetSchedule.td27 // each subtarget, define WriteRes and ReadAdvance to associate
306 // Define values common to ReadAdvance and SchedReadAdvance.
318 // A processor may define a ReadAdvance associated with a SchedRead
323 // A ReadAdvance may be associated with a list of SchedWrites
328 class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []>
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp961 Record *ReadAdvance = in GenSchedClassTables() local
963 if (!ReadAdvance) in GenSchedClassTables()
967 if (ReadAdvance->getValueAsBit("Unsupported")) { in GenSchedClassTables()
971 RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites"); in GenSchedClassTables()
985 RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles"); in GenSchedClassTables()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DSubtargetEmitter.cpp1158 Record *ReadAdvance = in GenSchedClassTables() local
1160 if (!ReadAdvance) in GenSchedClassTables()
1164 if (ReadAdvance->getValueAsBit("Unsupported")) { in GenSchedClassTables()
1168 RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites"); in GenSchedClassTables()
1182 RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles"); in GenSchedClassTables()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTargetSchedule.td27 // each subtarget, define WriteRes and ReadAdvance to associate
314 // Define values common to ReadAdvance and SchedReadAdvance.
326 // A processor may define a ReadAdvance associated with a SchedRead
331 // A ReadAdvance may be associated with a list of SchedWrites
336 class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []>
/external/llvm/lib/Target/ARM/
DARMSchedule.td38 // ReadAdvance read resources allow us to define "pipeline by-passes" or
55 // def : ReadAdvance<ReadAdvanceALUsr, 3>;

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