| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 57 RegPressure.resize(NumRC); in ResourcePriorityQueue()
59 std::fill(RegPressure.begin(), RegPressure.end(), 0); in ResourcePriorityQueue()
364 if ((RegPressure[RC->getID()] + in regPressureDelta()
366 (RegPressure[RC->getID()] + in regPressureDelta()
478 RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID()); in scheduledNode()
489 if (RegPressure[RC->getID()] > in scheduledNode()
491 RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID()); in scheduledNode()
492 else RegPressure[RC->getID()] = 0; in scheduledNode()
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| D | ScheduleDAGRRList.cpp | 1728 std::vector<unsigned> RegPressure; member in __anonacd034f10311::RegReductionPQBase
1747 RegPressure.resize(NumRC); in RegReductionPQBase()
1749 std::fill(RegPressure.begin(), RegPressure.end(), 0); in RegReductionPQBase()
1772 std::fill(RegPressure.begin(), RegPressure.end(), 0); in releaseState()
2058 unsigned RP = RegPressure[Id]; in dumpRegPressure()
2084 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
2103 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
2134 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2149 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2195 RegPressure[RCId] += Cost; in scheduledNode()
[all …]
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| D | SelectionDAGISel.cpp | 259 if (TLI->getSchedulingPreference() == Sched::RegPressure) in createDefaultScheduler()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 57 RegPressure.resize(NumRC); in ResourcePriorityQueue()
59 std::fill(RegPressure.begin(), RegPressure.end(), 0); in ResourcePriorityQueue()
377 if ((RegPressure[RC->getID()] + in regPressureDelta()
379 (RegPressure[RC->getID()] + in regPressureDelta()
491 RegPressure[RC->getID()] += numberRCValSuccInSU(SU, RC->getID()); in scheduledNode()
502 if (RegPressure[RC->getID()] > in scheduledNode()
504 RegPressure[RC->getID()] -= numberRCValPredInSU(SU, RC->getID()); in scheduledNode()
505 else RegPressure[RC->getID()] = 0; in scheduledNode()
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| D | ScheduleDAGRRList.cpp | 1639 std::vector<unsigned> RegPressure; member in __anone1ddf7990211::RegReductionPQBase
1659 RegPressure.resize(NumRC); in RegReductionPQBase()
1661 std::fill(RegPressure.begin(), RegPressure.end(), 0); in RegReductionPQBase()
1685 std::fill(RegPressure.begin(), RegPressure.end(), 0); in releaseState()
1934 unsigned RP = RegPressure[Id]; in dumpRegPressure()
1960 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
1979 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
2010 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2025 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2071 RegPressure[RCId] += Cost; in scheduledNode()
[all …]
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| D | SelectionDAGISel.cpp | 311 if (TLI->getSchedulingPreference() == Sched::RegPressure) in createDefaultScheduler()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | MachineLICM.cpp | 88 SmallVector<unsigned, 8> RegPressure; member in __anon0a0335650111::MachineLICM
138 RegPressure.clear(); in releaseMemory()
327 RegPressure.resize(NumRC); in runOnMachineFunction()
328 std::fill(RegPressure.begin(), RegPressure.end(), 0); in runOnMachineFunction()
637 BackTrace.push_back(RegPressure); in HoistRegion()
686 std::fill(RegPressure.begin(), RegPressure.end(), 0); in InitRegPressure()
714 RegPressure[RCId] += RCCost; in InitRegPressure()
719 RegPressure[RCId] += RCCost; in InitRegPressure()
721 RegPressure[RCId] -= RCCost; in InitRegPressure()
748 if (RCCost > RegPressure[RCId]) in UpdateRegPressure()
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | MachineLICM.cpp | 101 SmallVector<unsigned, 8> RegPressure; member in __anon3c58eeb90111::MachineLICM
149 RegPressure.clear(); in releaseMemory()
286 RegPressure.resize(NumRPS); in runOnMachineFunction()
287 std::fill(RegPressure.begin(), RegPressure.end(), 0); in runOnMachineFunction()
587 BackTrace.push_back(RegPressure); in EnterScope()
758 std::fill(RegPressure.begin(), RegPressure.end(), 0); in InitRegPressure()
781 if (static_cast<int>(RegPressure[Class]) < -RPIdAndCost.second) in UpdateRegPressure()
782 RegPressure[Class] = 0; in UpdateRegPressure()
784 RegPressure[Class] += RPIdAndCost.second; in UpdateRegPressure()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineLICM.cpp | 123 SmallVector<unsigned, 8> RegPressure; member in __anonbcfebb110111::MachineLICMBase
163 RegPressure.clear(); in releaseMemory()
330 RegPressure.resize(NumRPS); in runOnMachineFunction()
331 std::fill(RegPressure.begin(), RegPressure.end(), 0); in runOnMachineFunction()
636 BackTrace.push_back(RegPressure); in EnterScope()
808 std::fill(RegPressure.begin(), RegPressure.end(), 0); in InitRegPressure()
831 if (static_cast<int>(RegPressure[Class]) < -RPIdAndCost.second) in UpdateRegPressure()
832 RegPressure[Class] = 0; in UpdateRegPressure()
834 RegPressure[Class] += RPIdAndCost.second; in UpdateRegPressure()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 1528 std::vector<unsigned> RegPressure; member in __anon3c49a6c50411::RegReductionPQBase
1547 RegPressure.resize(NumRC); in RegReductionPQBase()
1549 std::fill(RegPressure.begin(), RegPressure.end(), 0); in RegReductionPQBase()
1573 std::fill(RegPressure.begin(), RegPressure.end(), 0); in releaseState()
1824 unsigned RP = RegPressure[Id]; in dumpRegPressure()
1850 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
1869 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
1901 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
1916 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
1963 RegPressure[RCId] += Cost; in ScheduledNode()
[all …]
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| D | SelectionDAGISel.cpp | 149 if (TLI.getSchedulingPreference() == Sched::RegPressure) in createDefaultScheduler()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ResourcePriorityQueue.h | 53 std::vector<unsigned> RegPressure; variable
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| D | MachineScheduler.h | 416 IntervalPressure RegPressure; variable
440 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure), in ScheduleDAGMILive()
460 const IntervalPressure &getRegPressure() const { return RegPressure; } in getRegPressure()
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| D | TargetLowering.h | 98 RegPressure, // Scheduling for lowest register pressure. enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineScheduler.h | 373 IntervalPressure RegPressure; variable
399 RPTracker(RegPressure), TopRPTracker(TopPressure), in ScheduleDAGMILive()
419 const IntervalPressure &getRegPressure() const { return RegPressure; } in getRegPressure()
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| D | ResourcePriorityQueue.h | 53 std::vector<unsigned> RegPressure; variable
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetMachine.h | 60 RegPressure, // Scheduling for lowest register pressure. enumerator
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 48 setSchedulingPreference(Sched::RegPressure); in WebAssemblyTargetLowering()
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 81 setSchedulingPreference(Sched::RegPressure); in SystemZTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 49 setSchedulingPreference(Sched::RegPressure); in WebAssemblyTargetLowering()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 73 RegPressure, // Scheduling for lowest register pressure. enumerator
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| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 80 setSchedulingPreference(Sched::RegPressure); in XCoreTargetLowering()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 746 setSchedulingPreference(Sched::RegPressure); in ARMTargetLowering()
980 return Sched::RegPressure; in getSchedulingPreference()
991 return Sched::RegPressure; in getSchedulingPreference()
999 return Sched::RegPressure; in getSchedulingPreference()
1004 return Sched::RegPressure; in getSchedulingPreference()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 45 setSchedulingPreference(Sched::RegPressure); in AVRTargetLowering()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1040 setSchedulingPreference(Sched::RegPressure); in ARMTargetLowering()
1297 return Sched::RegPressure; in getSchedulingPreference()
1308 return Sched::RegPressure; in getSchedulingPreference()
1316 return Sched::RegPressure; in getSchedulingPreference()
1321 return Sched::RegPressure; in getSchedulingPreference()
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