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Searched refs:ResVT (Results 1 – 25 of 39) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp608 EVT ResVT; in Select() local
614 ResVT = MVT::v2i64; in Select()
619 ResVT = MVT::v2i64; in Select()
635 dl, ResVT); in Select()
637 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT, in Select()
645 Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other, in Select()
650 Result = CurDAG->getMachineNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1); in Select()
687 EVT ResVT; in Select() local
695 ResVT = MVT::v2i32; in Select()
701 ResVT = MVT::v2i64; in Select()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp4458 EVT ResVT = N->getValueType(0); in ReplaceLoadVector() local
4461 assert(ResVT.isVector() && "Vector load must have vector type"); in ReplaceLoadVector()
4466 assert(ResVT.isSimple() && "Can only handle simple types"); in ReplaceLoadVector()
4467 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
4492 TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext())); in ReplaceLoadVector()
4502 EVT EltVT = ResVT.getVectorElementType(); in ReplaceLoadVector()
4503 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceLoadVector()
4573 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); in ReplaceLoadVector()
4580 SDValue BuildVec = DAG.getBuildVector(ResVT, DL, ScalarRes); in ReplaceLoadVector()
4603 EVT ResVT = N->getValueType(0); in ReplaceINTRINSIC_W_CHAIN() local
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/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp4289 EVT ResVT = N->getValueType(0); in ReplaceLoadVector() local
4292 assert(ResVT.isVector() && "Vector load must have vector type"); in ReplaceLoadVector()
4297 assert(ResVT.isSimple() && "Can only handle simple types"); in ReplaceLoadVector()
4298 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
4320 TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext())); in ReplaceLoadVector()
4330 EVT EltVT = ResVT.getVectorElementType(); in ReplaceLoadVector()
4331 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceLoadVector()
4376 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); in ReplaceLoadVector()
4382 SDValue BuildVec = DAG.getBuildVector(ResVT, DL, ScalarRes); in ReplaceLoadVector()
4405 EVT ResVT = N->getValueType(0); in ReplaceINTRINSIC_W_CHAIN() local
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp1723 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE() local
1761 return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags()); in SplitVecOp_VECREDUCE()
1766 EVT ResVT = N->getValueType(0); in SplitVecOp_UnaryOp() local
1772 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_UnaryOp()
1778 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
2222 EVT ResVT = N->getValueType(0); in SplitVecOp_FP_ROUND() local
2228 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_FP_ROUND()
2234 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in SplitVecOp_FP_ROUND()
3741 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), in WidenVecOp_SETCC() local
3745 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC, in WidenVecOp_SETCC()
DLegalizeDAG.cpp3906 EVT ResVT = Node->getValueType(0); in ExpandNode() local
3908 assert(OpVT == ResVT && in ExpandNode()
3915 if (TLI.isOperationLegal(RevRot, ResVT)) { in ExpandNode()
3917 Results.push_back(DAG.getNode(RevRot, dl, ResVT, Op0, Sub)); in ExpandNode()
3935 SDValue Or = DAG.getNode(ISD::OR, dl, ResVT, in ExpandNode()
3936 DAG.getNode(ShOpc, dl, ResVT, Op0, And0), in ExpandNode()
3937 DAG.getNode(HsOpc, dl, ResVT, Op0, And1)); in ExpandNode()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86FastISel.cpp1897 EVT ResVT = RVLocs[i].getValVT(); in DoSelectCall() local
1898 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in DoSelectCall()
1899 unsigned MemSize = ResVT.getSizeInBits()/8; in DoSelectCall()
1904 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; in DoSelectCall()
DX86ISelLowering.cpp5368 EVT ResVT = Op.getValueType(); in LowerMMXCONCAT_VECTORS() local
5370 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || in LowerMMXCONCAT_VECTORS()
5371 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); in LowerMMXCONCAT_VECTORS()
5377 unsigned NumElts = ResVT.getVectorNumElements(); in LowerMMXCONCAT_VECTORS()
5378 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); in LowerMMXCONCAT_VECTORS()
5379 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, in LowerMMXCONCAT_VECTORS()
5387 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); in LowerMMXCONCAT_VECTORS()
5394 EVT ResVT = Op.getValueType(); in LowerAVXCONCAT_VECTORS() local
5396 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); in LowerAVXCONCAT_VECTORS()
5400 unsigned NumElems = ResVT.getVectorNumElements(); in LowerAVXCONCAT_VECTORS()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp1016 EVT ResVT = N->getValueType(0); in SplitVecOp_UnaryOp() local
1022 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_UnaryOp()
1028 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
1191 EVT ResVT = N->getValueType(0); in SplitVecOp_FP_ROUND() local
1197 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_FP_ROUND()
1203 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in SplitVecOp_FP_ROUND()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp2758 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
2764 return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(), in lowerBITCAST()
2767 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
2783 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
4714 SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT, in combineExtract() argument
4741 return DAG.getUNDEF(ResVT); in combineExtract()
4771 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); in combineExtract()
4773 if (VT != ResVT) { in combineExtract()
4775 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op); in combineExtract()
4811 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp1562 EVT ResVT = N->getValueType(0); in SplitVecOp_UnaryOp() local
1568 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_UnaryOp()
1574 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
2012 EVT ResVT = N->getValueType(0); in SplitVecOp_FP_ROUND() local
2018 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_FP_ROUND()
2024 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in SplitVecOp_FP_ROUND()
3379 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), in WidenVecOp_SETCC() local
3383 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC, in WidenVecOp_SETCC()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp2888 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
2895 SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(), in lowerBITCAST()
2902 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
2918 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
5108 SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT, in combineExtract() argument
5136 return DAG.getUNDEF(ResVT); in combineExtract()
5166 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); in combineExtract()
5168 if (VT != ResVT) { in combineExtract()
5170 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op); in combineExtract()
5206 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp8537 bool AArch64TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
8539 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
8542 return (Index == 0 || Index == ResVT.getVectorNumElements()); in isExtractSubvectorCheap()
9805 EVT ResVT = N->getValueType(0); in performExtendCombine() local
9806 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT)) in performExtendCombine()
9813 if (!ResVT.isSimple() || !SrcVT.isSimple()) in performExtendCombine()
9831 unsigned NumElements = ResVT.getVectorNumElements(); in performExtendCombine()
9834 ResVT.getVectorElementType(), NumElements / 2); in performExtendCombine()
9847 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in performExtendCombine()
10773 EVT ResVT = N->getValueType(0); in performVSelectCombine() local
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DAArch64ISelLowering.h375 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp8640 EVT ResVT = N->getValueType(0); in performExtendCombine() local
8641 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT)) in performExtendCombine()
8648 if (!ResVT.isSimple() || !SrcVT.isSimple()) in performExtendCombine()
8666 unsigned NumElements = ResVT.getVectorNumElements(); in performExtendCombine()
8669 ResVT.getVectorElementType(), NumElements / 2); in performExtendCombine()
8682 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in performExtendCombine()
9754 EVT ResVT = N->getValueType(0); in performVSelectCombine() local
9758 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits()) in performVSelectCombine()
9767 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
9779 EVT ResVT = N->getValueType(0); in performSelectCombine() local
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp4698 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
4700 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
4705 if (ResVT.getVectorElementType() == MVT::i1) in isExtractSubvectorCheap()
4706 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) && in isExtractSubvectorCheap()
4707 (Index == ResVT.getVectorNumElements())); in isExtractSubvectorCheap()
4709 return (Index % ResVT.getVectorNumElements()) == 0; in isExtractSubvectorCheap()
8688 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
8690 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
8691 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide"); in LowerAVXCONCAT_VECTORS()
8712 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(), in LowerAVXCONCAT_VECTORS()
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DX86FastISel.cpp3597 EVT ResVT = VA.getValVT(); in fastLowerCall() local
3598 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3599 unsigned MemSize = ResVT.getSizeInBits()/8; in fastLowerCall()
3604 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; in fastLowerCall()
DX86ISelLowering.h1037 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelLowering.h492 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp4159 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, in isExtractSubvectorCheap() argument
4161 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
4164 return (Index == 0 || Index == ResVT.getVectorNumElements()); in isExtractSubvectorCheap()
6902 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
6904 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
6905 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide"); in LowerAVXCONCAT_VECTORS()
6909 unsigned NumElems = ResVT.getVectorNumElements(); in LowerAVXCONCAT_VECTORS()
6910 if (ResVT.is256BitVector()) in LowerAVXCONCAT_VECTORS()
6911 return concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); in LowerAVXCONCAT_VECTORS()
6914 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(), in LowerAVXCONCAT_VECTORS()
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DX86ISelLowering.h947 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
DX86FastISel.cpp3381 EVT ResVT = VA.getValVT(); in fastLowerCall() local
3382 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3383 unsigned MemSize = ResVT.getSizeInBits()/8; in fastLowerCall()
3388 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; in fastLowerCall()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelLowering.cpp3582 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
3600 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
3608 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
3620 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
3626 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
3632 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
3638 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp6859 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
6877 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
6880 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6890 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
6899 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6913 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6916 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6923 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
6929 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6935 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp2368 EVT ResVT = VecVT.changeVectorElementTypeToInteger(); in trySETCC() local
2370 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0); in trySETCC()
2372 ResVT, VCmp, VCmp); in trySETCC()
2376 CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS); in trySETCC()
DPPCISelLowering.cpp6293 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
6310 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
6313 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6322 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
6330 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6343 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6346 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6353 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
6359 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6365 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
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