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/external/llvm/lib/Target/Hexagon/
DHexagonInstrAlias.td43 // Alias of: memXX($Rs+#XX) = $Rt to memXX($Rs) = $Rt
44 def : InstAlias<"memb($Rs) = $Rt",
45 (S2_storerb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
47 def : InstAlias<"memh($Rs) = $Rt",
48 (S2_storerh_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
50 def : InstAlias<"memh($Rs) = $Rt.h",
51 (S2_storerf_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
53 def : InstAlias<"memw($Rs) = $Rt",
54 (S2_storeri_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
56 def : InstAlias<"memb($Rs) = $Rt.new",
[all …]
DHexagonInstrInfoVector.td177 : Pat <(Op Value:$Rs, I32:$Rt),
178 (MI Value:$Rs, I32:$Rt)>;
207 : Pat <(i1 (Op Value:$Rs, Value:$Rt)),
208 (MI Value:$Rs, Value:$Rt)>;
224 : Pat <(OutTy (Op InVal:$Rs, InVal:$Rt)),
225 (MI InVal:$Rs, InVal:$Rt)>;
242 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
244 [(set V2I32:$Rd, (mul V2I32:$Rs, V2I32:$Rt))]>;
248 (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt),
250 [(set V2I32:$Rd, (add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)))],
[all …]
DHexagonIntrinsics.td39 : Pat<(IntID ImmPred:$Is, I32:$Rt),
40 (MI ImmPred:$Is, I32:$Rt)>;
47 : Pat<(IntID I32:$Rs, I64:$Rt),
48 (MI I32:$Rs, I64:$Rt)>;
51 : Pat <(IntID I32:$Rs, I32:$Rt),
52 (MI I32:$Rs, I32:$Rt)>;
55 : Pat <(IntID I64:$Rs, I64:$Rt),
56 (MI I64:$Rs, I64:$Rt)>;
59 : Pat <(IntID I32:$Rs, I32:$Rt),
60 (MI (C2_tfrrp I32:$Rs), (C2_tfrrp I32:$Rt))>;
[all …]
DHexagonSystemInst.td24 bits<5> Rt;
31 let Inst{12-8} = Rt;
42 bits<5> Rt;
49 let Inst{12-8} = Rt;
54 let isSolo = 1, Rs = 0, Rt = 0, Rd = 0 in {
59 let Rt = 0, Rd = 0 in {
71 def Y4_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, IntRegs:$Rt),
72 "l2fetch($Rs, $Rt)", [], 0b011, 0b000, 0b0>;
73 def Y5_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, DoubleRegs:$Rt),
74 "l2fetch($Rs, $Rt)", [], 0b011, 0b010, 0b0>;
DHexagonAsmPrinter.cpp330 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local
331 assert (Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
332 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
337 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
341 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
342 assert (Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
343 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
348 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
353 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
354 assert (Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
[all …]
/external/llvm/test/CodeGen/Hexagon/
Dalu64.ll5 define i32 @test00(i64 %Rs, i64 %Rt) #0 {
7 %0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt)
13 define i32 @test01(i64 %Rs, i64 %Rt) #0 {
15 %0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt)
21 define i32 @test02(i64 %Rs, i64 %Rt) #0 {
23 %0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt)
29 define i32 @test10(i32 %Rs, i32 %Rt) #0 {
31 %0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt)
37 define i32 @test11(i32 %Rs, i32 %Rt) #0 {
39 %0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dalu64.ll5 define i32 @test00(i64 %Rs, i64 %Rt) #0 {
7 %0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt)
13 define i32 @test01(i64 %Rs, i64 %Rt) #0 {
15 %0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt)
21 define i32 @test02(i64 %Rs, i64 %Rt) #0 {
23 %0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt)
29 define i32 @test10(i32 %Rs, i32 %Rt) #0 {
31 %0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt)
37 define i32 @test11(i32 %Rs, i32 %Rt) #0 {
39 %0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt)
[all …]
/external/vixl/test/aarch32/config/
Dcond-rd-memop-rs-a32.json29 "Ldr", // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
30 // LDR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
31 // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
32 "Ldrb", // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
33 // LDRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
34 // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
35 "Ldrh", // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1
36 // LDRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<Rm> ; A1
37 // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>]! ; A1
38 "Ldrsb", // LDRSB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1
[all …]
Dcond-rd-memop-immediate-8192-a32.json29 "Ldr", // LDR{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
30 // LDR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_3> ; A1
31 // LDR{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}]! ; A1
32 "Ldrb", // LDRB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
33 // LDRB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_3> ; A1
34 // LDRB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}]! ; A1
35 "Str", // STR{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
36 // STR{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_3> ; A1
37 // STR{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}]! ; A1
38 "Strb" // STRB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
[all …]
Dcond-rd-memop-rs-shift-amount-1to31-a32.json29 "Ldr", // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
30 // LDR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
31 // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
32 "Ldrb", // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
33 // LDRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
34 // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
35 "Str", // STR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
36 // STR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1
37 // STR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1
38 "Strb" // STRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1
[all …]
Dcond-rd-memop-immediate-512-a32.json29 "Ldrh", // LDRH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
30 // LDRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_3> ; A1
31 // LDRH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}]! ; A1
32 "Ldrsh", // LDRSH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_2>}] ; A1
33 // LDRSH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_2> ; A1
34 // LDRSH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_2>}]! ; A1
35 "Ldrsb", // LDRSB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_2>}] ; A1
36 // LDRSB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_2> ; A1
37 // LDRSB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_2>}]! ; A1
38 "Strh" // STRH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
[all …]
/external/eigen/Eigen/src/Geometry/
DUmeyama.h134 TransformationMatrixType Rt = TransformationMatrixType::Identity(m+1,m+1); variable
143 Rt.block(0,0,m,m).noalias() = svd.matrixU() * S.asDiagonal() * svd.matrixV().transpose();
151 Rt.col(m).head(m) = dst_mean;
152 Rt.col(m).head(m).noalias() -= c*Rt.topLeftCorner(m,m)*src_mean;
153 Rt.block(0,0,m,m) *= c;
157 Rt.col(m).head(m) = dst_mean;
158 Rt.col(m).head(m).noalias() -= Rt.topLeftCorner(m,m)*src_mean;
161 return Rt;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonPatterns.td47 // 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
222 def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
223 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>;
276 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
277 (MI RsPred:$Rs, RtPred:$Rt)>;
286 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)),
287 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>;
622 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
623 (Output RsPred:$Rs, RtPred:$Rt)>;
626 : OutPatFrag<(ops node:$Rs, node:$Rt),
[all …]
DHexagonIntrinsics.td39 : Pat<(IntID ImmPred:$Is, I32:$Rt),
40 (MI ImmPred:$Is, I32:$Rt)>;
47 : Pat<(IntID I32:$Rs, I64:$Rt),
48 (MI I32:$Rs, I64:$Rt)>;
51 : Pat <(IntID I32:$Rs, I32:$Rt),
52 (MI I32:$Rs, I32:$Rt)>;
55 : Pat <(IntID I64:$Rs, I64:$Rt),
56 (MI I64:$Rs, I64:$Rt)>;
59 : Pat <(IntID I32:$Rs, I32:$Rt),
60 (MI (C2_tfrrp I32:$Rs), (C2_tfrrp I32:$Rt))>;
[all …]
DHexagonPatternsHVX.td101 def: Pat<(ResType (Load I32:$Rt)),
102 (MI I32:$Rt, 0)>;
103 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))),
104 (MI I32:$Rt, imm:$s)>;
117 def: Pat<(ResType (Load (valignaddr I32:$Rt))),
118 (MI I32:$Rt, 0)>;
119 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
120 (MI I32:$Rt, imm:$Off)>;
143 def: Pat<(Store Value:$Vs, I32:$Rt),
144 (MI I32:$Rt, 0, Value:$Vs)>;
[all …]
DHexagonPatternsV65.td13 (ins IntRegs:$_dst_, IntRegs:$Rt,
22 (ins IntRegs:$_dst_, IntRegs:$Rt,
31 (ins IntRegs:$_dst_, IntRegs:$Rt,
44 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
53 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
62 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td983 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
984 opc, ".w\t$Rt, $addr",
985 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]>,
987 bits<4> Rt;
995 let Inst{15-12} = Rt;
1000 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
1001 opc, "\t$Rt, $addr",
1002 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]>,
1004 bits<4> Rt;
1013 let Inst{15-12} = Rt;
[all …]
DARMInstrInfo.td1834 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1835 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1836 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1837 bits<4> Rt;
1841 let Inst{15-12} = Rt;
1844 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1845 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1846 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1847 bits<4> Rt;
1852 let Inst{15-12} = Rt;
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td977 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
978 opc, ".w\t$Rt, $addr",
979 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
980 bits<4> Rt;
988 let Inst{15-12} = Rt;
993 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
994 opc, "\t$Rt, $addr",
995 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
996 bits<4> Rt;
1005 let Inst{15-12} = Rt;
[all …]
DARMInstrInfo.td1730 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1731 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1732 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1733 bits<4> Rt;
1737 let Inst{15-12} = Rt;
1740 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1741 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1742 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1743 bits<4> Rt;
1748 let Inst{15-12} = Rt;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp674 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
678 if (Rs >= Rt) { in DecodeAddiGroupBranch()
681 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
692 Rt))); in DecodeAddiGroupBranch()
702 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local
706 if (Rs >= Rt) { in DecodePOP35GroupBranchMMR6()
709 Rt))); in DecodePOP35GroupBranchMMR6()
713 } else if (Rs != 0 && Rs < Rt) { in DecodePOP35GroupBranchMMR6()
718 Rt))); in DecodePOP35GroupBranchMMR6()
723 Rt))); in DecodePOP35GroupBranchMMR6()
[all …]
/external/capstone/arch/Mips/
DMipsDisassembler.c537 uint32_t Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch_4() local
541 if (Rs >= Rt) { in DecodeAddiGroupBranch_4()
544 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch_4()
553 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); in DecodeAddiGroupBranch_4()
573 uint32_t Rt = fieldFromInstruction(insn, 16, 5); in DecodeDaddiGroupBranch_4() local
577 if (Rs >= Rt) { in DecodeDaddiGroupBranch_4()
580 } else if (Rs != 0 && Rs < Rt) { in DecodeDaddiGroupBranch_4()
589 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); in DecodeDaddiGroupBranch_4()
610 uint32_t Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezlGroupBranch_4() local
614 if (Rt == 0) in DecodeBlezlGroupBranch_4()
[all …]
/external/capstone/arch/AArch64/
DAArch64Disassembler.c943 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local
952 MCOperand_CreateImm0(Inst, Rt); in DecodeUnsignedLdStInstruction()
962 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
969 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
973 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
977 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
981 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
985 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
989 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1007 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSignedLdStInstruction() local
[all …]
/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp603 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
607 if (Rs >= Rt) { in DecodeAddiGroupBranch()
610 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
621 Rt))); in DecodeAddiGroupBranch()
631 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local
635 if (Rs >= Rt) { in DecodePOP35GroupBranchMMR6()
638 Rt))); in DecodePOP35GroupBranchMMR6()
641 } else if (Rs != 0 && Rs < Rt) { in DecodePOP35GroupBranchMMR6()
646 Rt))); in DecodePOP35GroupBranchMMR6()
650 Rt))); in DecodePOP35GroupBranchMMR6()
[all …]
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp207 MCOperand Rs, Rt; in getCompoundInsn() local
217 Rt = L.getOperand(0); in getCompoundInsn()
222 CompoundInsn->addOperand(Rt); in getCompoundInsn()
228 Rt = L.getOperand(0); in getCompoundInsn()
234 CompoundInsn->addOperand(Rt); in getCompoundInsn()
243 Rt = L.getOperand(2); in getCompoundInsn()
249 CompoundInsn->addOperand(Rt); in getCompoundInsn()
256 Rt = L.getOperand(2); in getCompoundInsn()
262 CompoundInsn->addOperand(Rt); in getCompoundInsn()
269 Rt = L.getOperand(2); in getCompoundInsn()
[all …]

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