Searched refs:SCD_R6 (Results 1 – 20 of 20) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | atomicrmx.ll | 23 ;CHK64: SCD_R6
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| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | atomicrmx.ll | 23 ;CHK64: SCD_R6
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSERegisterInfo.cpp | 99 case Mips::SCD_R6: in getLoadStoreOffsetSizeInBits()
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| D | MipsExpandPseudo.cpp | 237 SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in expandAtomicCmpSwap()
512 SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in expandAtomicBinOp()
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| D | Mips64r6InstrInfo.td | 151 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 588 SCD_R6 = ((4U << 3) + 7), enumerator
1803 case SCD_R6: { in InstructionType()
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| D | disasm-mips64.cc | 1995 case SCD_R6: { in DecodeTypeImmediateSPECIAL3()
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| D | assembler-mips64.cc | 2489 GenInstrImmediate(SPECIAL3, rs.rm(), rd, rs.offset_, 0, SCD_R6); in scd()
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| D | simulator-mips64.cc | 7164 case SCD_R6: { in DecodeTypeImmediate()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64r6InstrInfo.td | 123 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
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| D | MipsISelLowering.cpp | 1135 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in emitAtomicBinary()
1422 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in emitAtomicCmpSwap()
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1814 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ in DecodeSpecial3LlSc()
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1385 1756727U, // SCD_R6
3099 0U, // SCD_R6
4631 // SC, SCD, SCD_R6, SC_MM, SC_R6
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| D | MipsGenDisassemblerTables.inc | 4018 /* 1619 */ MCD_OPC_Decode, 216, 10, 223, 1, // Opcode: SCD_R6
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 2043 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ in DecodeSpecial3LlSc()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 3433 4493333U, // SCD_R6
6064 0U, // SCD_R6
6664 // SC, SC64, SC64_R6, SCD, SCD_R6, SCE, SCE_MM, SC_MM, SC_MMR6, SC_R6
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| D | MipsGenMCCodeEmitter.inc | 2218 UINT64_C(2080374823), // SCD_R6
6448 case Mips::SCD_R6:
9944 Feature_HasStdEnc | Feature_HasMips32r6 | 0, // SCD_R6 = 2205
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| D | MipsGenInstrInfo.inc | 2220 SCD_R6 = 2205,
6265 …deledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2205 = SCD_R6
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| D | MipsGenDisassemblerTables.inc | 6602 /* 2057 */ MCD::OPC_Decode, 157, 17, 228, 2, // Opcode: SCD_R6
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| D | MipsGenAsmMatcher.inc | 7136 …{ 7882 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasS…
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