/external/pcre/dist2/src/sljit/ |
D | sljitNativeSPARC_32.c | 108 FAIL_IF(push_inst(compiler, SMUL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst))); in emit_single_op()
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D | sljitNativeSPARC_common.c | 192 #define SMUL (OPC1(0x2) | OPC3(0x0b)) macro 818 …FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? UMUL : SMUL) | D(SLJIT_R0) | S1(SLJIT_R0) | S2(… in sljit_emit_op0() 840 FAIL_IF(push_inst(compiler, SMUL | D(SLJIT_R1) | S1(SLJIT_R0) | S2(SLJIT_R1), DR(SLJIT_R1))); in sljit_emit_op0()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86ISelLowering.h | 235 ADD, SUB, ADC, SBB, SMUL, enumerator
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D | X86ISelLowering.cpp | 8601 Opc == X86ISD::SMUL || in isX86LogicalCmp() 8792 Cond.getOpcode() == X86ISD::SMUL || in LowerBRCOND() 10088 BaseOp = X86ISD::SMUL; in LowerXALUO() 10701 case X86ISD::SMUL: return "X86ISD::SMUL"; in getTargetNodeName() 12318 case X86ISD::SMUL: in computeMaskedBitsForTargetNode()
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D | X86InstrInfo.td | 212 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
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D | X86GenDAGISel.inc | 25152 /*SwitchOpcode*/ 107|128,3/*491*/, TARGET_VAL(X86ISD::SMUL),// ->52068
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.h | 342 ADD, SUB, ADC, SBB, SMUL, enumerator
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D | X86FastISel.cpp | 2740 BaseOpc = X86ISD::SMUL; CondOpc = X86::SETOr; break; in fastLowerIntrinsicCall() 2793 } else if (BaseOpc == X86ISD::SMUL && !ResultReg) { in fastLowerIntrinsicCall()
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D | X86ISelLowering.cpp | 15686 Opc == X86ISD::SMUL || in isX86LogicalCmp() 15918 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; in LowerSELECT() 16562 Cond.getOpcode() == X86ISD::SMUL || in LowerBRCOND() 16628 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; in LowerBRCOND() 20517 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL; in LowerXALUO() 22206 case X86ISD::SMUL: return "X86ISD::SMUL"; in getTargetNodeName() 24621 case X86ISD::SMUL: in computeKnownBitsForTargetNode()
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D | X86InstrInfo.td | 241 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86ISelLowering.h | 352 ADD, SUB, ADC, SBB, SMUL, enumerator
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D | X86FastISel.cpp | 2923 BaseOpc = X86ISD::SMUL; CondOpc = X86::SETOr; break; in fastLowerIntrinsicCall() 2976 } else if (BaseOpc == X86ISD::SMUL && !ResultReg) { in fastLowerIntrinsicCall()
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D | X86ISelLowering.cpp | 18792 Opc == X86ISD::SBB || Opc == X86ISD::SMUL || in isX86LogicalCmp() 19071 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; in LowerSELECT() 19675 Cond.getOpcode() == X86ISD::SMUL || in LowerBRCOND() 19741 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; in LowerBRCOND() 24079 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL; in LowerXALUO() 26030 case X86ISD::SMUL: return "X86ISD::SMUL"; in getTargetNodeName()
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D | X86InstrInfo.td | 253 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
D | SparcInstrInfo.td | 490 defm SMUL : F3_12 <"smul", 0b001011, mul>;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
D | SparcInstrInfo.td | 742 defm SMUL : F3_12<"smul", 0b001011, smullohi, IntRegs, i32, simm13Op, IIC_iu_smul>;
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/external/llvm/lib/Target/Sparc/ |
D | SparcInstrInfo.td | 738 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op, IIC_iu_smul>;
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMInstrFormats.td | 725 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
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D | ARMInstrInfo.td | 3693 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrFormats.td | 854 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
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D | ARMInstrInfo.td | 4102 defm SMUL : AI_smul<"smul">;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMInstrFormats.td | 874 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
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D | ARMInstrInfo.td | 4310 defm SMUL : AI_smul<"smul">;
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