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Searched refs:SPR (Results 1 – 25 of 50) sorted by relevance

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/external/llvm/lib/Target/ARM/
DARMInstrVFP.td105 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
107 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]> {
113 def VLDRH : AHI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5fp16:$addr),
124 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
126 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]> {
132 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5fp16:$addr),
343 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
345 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
353 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
365 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
[all …]
DARMRegisterInfo.td272 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
273 let AltOrders = [(add (decimate SPR, 2), SPR),
274 (add (decimate SPR, 4),
275 (decimate SPR, 2),
276 (decimate (rotl SPR, 1), 4),
277 (decimate (rotl SPR, 1), 2))];
283 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
303 // 32-bit SPR subregs).
320 // Subset of QPR that have 32-bit SPR subregs.
DARMInstrNEON.td4219 def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4221 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4223 def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4225 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
5935 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
5937 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5938 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
5940 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5947 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
5948 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrVFP.td75 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
77 [(set SPR:$Sd, (load addrmode5:$addr))]> {
89 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
91 [(store SPR:$Sd, addrmode5:$addr)]> {
206 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
208 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
220 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
222 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
234 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
236 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
[all …]
DARMRegisterInfo.td265 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)>;
267 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
269 def SPR_8 : RegisterClass<"ARM", [f32], 32, (trunc SPR, 16)>;
283 // 32-bit SPR subregs).
286 let SubRegClasses = [(SPR ssub_0, ssub_1)];
305 // Subset of QPR that have 32-bit SPR subregs.
308 let SubRegClasses = [(SPR ssub_0, ssub_1, ssub_2, ssub_3),
329 // Subset of QQPR that have 32-bit SPR subregs.
331 let SubRegClasses = [(SPR ssub_0, ssub_1, ssub_2, ssub_3),
DARMInstrNEON.td4487 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4489 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4490 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4492 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4499 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4500 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4503 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4504 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4612 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4613 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrVFP.td125 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
127 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]> {
144 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
146 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]> {
344 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
346 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>,
369 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
371 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>,
394 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
396 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>,
[all …]
DARMRegisterInfo.td298 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
299 let AltOrders = [(add (decimate SPR, 2), SPR),
300 (add (decimate SPR, 4),
301 (decimate SPR, 2),
302 (decimate (rotl SPR, 1), 4),
303 (decimate (rotl SPR, 1), 2))];
311 let AltOrders = [(add (decimate HPR, 2), SPR),
322 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
345 // 32-bit SPR subregs).
367 // Subset of QPR that have 32-bit SPR subregs.
DARMRegisterBanks.td14 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
DARMInstrNEON.td4310 def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4312 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4314 def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4316 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
6210 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
6212 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
6213 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
6215 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
6222 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
6223 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCRegisterInfo.td40 // SPR - One of the 32-bit special-purpose registers
41 class SPR<bits<10> num, string n> : PPCReg<n> {
250 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
252 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
255 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
256 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
259 def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[109]>;
262 // (which really is SPR register 1); this is the only bit interesting to a
264 def CARRY: SPR<1, "ca">;
273 // Also, in the architecture it is not really a SPR; 512 is arbitrary.
[all …]
DPPCInstrFormats.td525 bits<10> SPR;
528 let Inst{11} = SPR{4};
529 let Inst{12} = SPR{3};
530 let Inst{13} = SPR{2};
531 let Inst{14} = SPR{1};
532 let Inst{15} = SPR{0};
533 let Inst{16} = SPR{9};
534 let Inst{17} = SPR{8};
535 let Inst{18} = SPR{7};
536 let Inst{19} = SPR{6};
[all …]
DPPCJITInfo.cpp36 #define BUILD_MTSPR(RS,SPR) \ argument
37 ((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1))
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td48 // SPR - One of the 32-bit special-purpose registers
49 class SPR<bits<10> num, string n> : PPCReg<n> {
213 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
215 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
218 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
219 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
222 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
228 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
230 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
233 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
DPPCInstrFormats.td1553 bits<10> SPR;
1556 let Inst{11} = SPR{4};
1557 let Inst{12} = SPR{3};
1558 let Inst{13} = SPR{2};
1559 let Inst{14} = SPR{1};
1560 let Inst{15} = SPR{0};
1561 let Inst{16} = SPR{9};
1562 let Inst{17} = SPR{8};
1563 let Inst{18} = SPR{7};
1564 let Inst{19} = SPR{6};
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td42 // SPR - One of the 32-bit special-purpose registers
43 class SPR<bits<10> num, string n> : PPCReg<n> {
205 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
207 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
210 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
211 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
214 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
217 // (which really is SPR register 1); this is the only bit interesting to a
219 def CARRY: SPR<1, "ca">, DwarfRegNum<[76]>;
DPPCInstrFormats.td1345 bits<10> SPR;
1348 let Inst{11} = SPR{4};
1349 let Inst{12} = SPR{3};
1350 let Inst{13} = SPR{2};
1351 let Inst{14} = SPR{1};
1352 let Inst{15} = SPR{0};
1353 let Inst{16} = SPR{9};
1354 let Inst{17} = SPR{8};
1355 let Inst{18} = SPR{7};
1356 let Inst{19} = SPR{6};
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/GlobalISel/
Darm-select-copy_to_regclass-of-fptosi.mir8 # G_FPTOSI selects to a (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR), where
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc9491 …// Src: (st (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a), addrmode5:{ *:[i32] }:$ptr)<<P:Predicate_…
9492 … // Dst: (VSTRS (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), addrmode5:{ *:[i32] }:$ptr)
9537 …// Src: (st (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a), addrmode5:{ *:[i32] }:$ptr)<<P:Predicate_…
9538 … // Dst: (VSTRS (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), addrmode5:{ *:[i32] }:$ptr)
9902 …// Src: (st SPR:{ *:[f32] }:$Sd, addrmode5:{ *:[i32] }:$addr)<<P:Predicate_unindexedstore>><<P:Pre…
9903 // Dst: (VSTRS SPR:{ *:[f32] }:$Sd, addrmode5:{ *:[i32] }:$addr)
12443 …v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$Rn, SPR:{ *:[i32] }), ssub_…
12452 … // Src: (intrinsic_wo_chain:{ *:[f32] } 1103:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) - Complexity = 8
12453 // Dst: (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
12509 … // Src: (intrinsic_wo_chain:{ *:[f32] } 1218:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) - Complexity = 8
[all …]
DARMGenGlobalISel.inc6776 … // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn) => (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn)
8655 …(intrinsic_wo_chain:{ *:[f32] } 1103:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VRINTNS:{ *:[f32] } …
8705 …(intrinsic_wo_chain:{ *:[f32] } 1218:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOSIRS:{ *:[f32] } …
8741 …(intrinsic_wo_chain:{ *:[f32] } 1219:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOUIRS:{ *:[f32] } …
21788 …// (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f3…
22044 …// (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f3…
22301 …l:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b) => (VNMULS:{ *:[f32] } …
22321 …// (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (VNMULS:{ *:[…
22337 …// (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f3…
22527 …SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/
DInstCombineSelect.cpp801 SelectPatternResult SPR = matchSelectPattern(&Sel, LHS, RHS); in canonicalizeMinMaxWithConstant() local
802 if (!SelectPatternResult::isMinOrMax(SPR.Flavor)) in canonicalizeMinMaxWithConstant()
806 ICmpInst::Predicate CanonicalPred = getMinMaxPred(SPR.Flavor); in canonicalizeMinMaxWithConstant()
1764 SelectPatternResult SPR = matchSelectPattern(&SI, LHS, RHS, &CastOp); in visitSelectInst() local
1765 auto SPF = SPR.Flavor; in visitSelectInst()
1779 CmpInst::Predicate Pred = getMinMaxPred(SPF, SPR.Ordered); in visitSelectInst()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeRegisterInfo.td114 def SPR : RegisterClass<"MBlaze", [i32], 32, (add
/external/llvm/lib/Transforms/InstCombine/
DInstCombineSelect.cpp1105 SelectPatternResult SPR = matchSelectPattern(&SI, LHS, RHS, &CastOp); in visitSelectInst() local
1106 auto SPF = SPR.Flavor; in visitSelectInst()
1112 CmpInst::Predicate Pred = getCmpPredicateForMinMax(SPF, SPR.Ordered); in visitSelectInst()
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc8799 // (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)
9448 // (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)
9830 // (VCMPZS SPR:$val, pred:$p)
9848 // (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)
9885 // (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)
9947 // (VRINTAS SPR:$Sd, SPR:$Sm)
9991 // (VRINTMS SPR:$Sd, SPR:$Sm)
10035 // (VRINTNS SPR:$Sd, SPR:$Sm)
10079 // (VRINTPS SPR:$Sd, SPR:$Sm)
10101 // (VRINTRS SPR:$Sd, SPR:$Sm, pred:$p)
[all …]
/external/llvm/lib/Analysis/
DLazyValueInfo.cpp914 SelectPatternResult SPR = matchSelectPattern(SI, LHS, RHS); in solveBlockValueSelect() local
917 if (SelectPatternResult::isMinOrMax(SPR.Flavor) && in solveBlockValueSelect()
919 switch (SPR.Flavor) { in solveBlockValueSelect()

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